1*83d290c5STom Rini/* SPDX-License-Identifier: GPL-2.0+ */ 2a47a12beSStefan Roese/* 3a47a12beSStefan Roese * Copyright 2004, 2007, 2008 Freescale Semiconductor. 4a47a12beSStefan Roese * Srikanth Srinivasan <srikanth.srinivaan@freescale.com> 5a47a12beSStefan Roese */ 6a47a12beSStefan Roese#include <config.h> 7a47a12beSStefan Roese#include <mpc86xx.h> 8a47a12beSStefan Roese 9a47a12beSStefan Roese#include <ppc_asm.tmpl> 10a47a12beSStefan Roese#include <ppc_defs.h> 11a47a12beSStefan Roese 12a47a12beSStefan Roese#include <asm/cache.h> 13a47a12beSStefan Roese#include <asm/mmu.h> 14a47a12beSStefan Roese 15a47a12beSStefan Roese/* If this is a multi-cpu system then we need to handle the 16a47a12beSStefan Roese * 2nd cpu. The assumption is that the 2nd cpu is being 17a47a12beSStefan Roese * held in boot holdoff mode until the 1st cpu unlocks it 18a47a12beSStefan Roese * from Linux. We'll do some basic cpu init and then pass 19a47a12beSStefan Roese * it to the Linux Reset Vector. 20a47a12beSStefan Roese * Sri: Much of this initialization is not required. Linux 21a47a12beSStefan Roese * rewrites the bats, and the sprs and also enables the L1 cache. 22a47a12beSStefan Roese * 23a47a12beSStefan Roese * Core 0 must copy this to a 1M aligned region and set BPTR 24a47a12beSStefan Roese * to point to it. 25a47a12beSStefan Roese */ 26a47a12beSStefan Roese .align 12 27a47a12beSStefan Roese.globl __secondary_start_page 28a47a12beSStefan Roese__secondary_start_page: 29a47a12beSStefan Roese .space 0x100 /* space over to reset vector loc */ 30a47a12beSStefan Roese mfspr r0, MSSCR0 31a47a12beSStefan Roese andi. r0, r0, 0x0020 32a47a12beSStefan Roese rlwinm r0,r0,27,31,31 33a47a12beSStefan Roese mtspr PIR, r0 34a47a12beSStefan Roese 35a47a12beSStefan Roese /* Invalidate BATs */ 36a47a12beSStefan Roese li r0, 0 37a47a12beSStefan Roese mtspr IBAT0U, r0 38a47a12beSStefan Roese mtspr IBAT1U, r0 39a47a12beSStefan Roese mtspr IBAT2U, r0 40a47a12beSStefan Roese mtspr IBAT3U, r0 41a47a12beSStefan Roese mtspr IBAT4U, r0 42a47a12beSStefan Roese mtspr IBAT5U, r0 43a47a12beSStefan Roese mtspr IBAT6U, r0 44a47a12beSStefan Roese mtspr IBAT7U, r0 45a47a12beSStefan Roese isync 46a47a12beSStefan Roese mtspr DBAT0U, r0 47a47a12beSStefan Roese mtspr DBAT1U, r0 48a47a12beSStefan Roese mtspr DBAT2U, r0 49a47a12beSStefan Roese mtspr DBAT3U, r0 50a47a12beSStefan Roese mtspr DBAT4U, r0 51a47a12beSStefan Roese mtspr DBAT5U, r0 52a47a12beSStefan Roese mtspr DBAT6U, r0 53a47a12beSStefan Roese mtspr DBAT7U, r0 54a47a12beSStefan Roese isync 55a47a12beSStefan Roese sync 56a47a12beSStefan Roese 57a47a12beSStefan Roese /* enable extended addressing */ 58a47a12beSStefan Roese mfspr r0, HID0 59a47a12beSStefan Roese lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h 60a47a12beSStefan Roese ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l 61a47a12beSStefan Roese mtspr HID0, r0 62a47a12beSStefan Roese sync 63a47a12beSStefan Roese isync 64a47a12beSStefan Roese 65a47a12beSStefan Roese#ifdef CONFIG_SYS_L2 66a47a12beSStefan Roese /* init the L2 cache */ 67a47a12beSStefan Roese addis r3, r0, L2_INIT@h 68a47a12beSStefan Roese ori r3, r3, L2_INIT@l 69a47a12beSStefan Roese sync 70a47a12beSStefan Roese mtspr l2cr, r3 71a47a12beSStefan Roese#ifdef CONFIG_ALTIVEC 72a47a12beSStefan Roese dssall 73a47a12beSStefan Roese#endif 74a47a12beSStefan Roese /* invalidate the L2 cache */ 75a47a12beSStefan Roese mfspr r3, l2cr 76a47a12beSStefan Roese rlwinm. r3, r3, 0, 0, 0 77a47a12beSStefan Roese beq 1f 78a47a12beSStefan Roese 79a47a12beSStefan Roese mfspr r3, l2cr 80a47a12beSStefan Roese rlwinm r3, r3, 0, 1, 31 81a47a12beSStefan Roese 82a47a12beSStefan Roese#ifdef CONFIG_ALTIVEC 83a47a12beSStefan Roese dssall 84a47a12beSStefan Roese#endif 85a47a12beSStefan Roese sync 86a47a12beSStefan Roese mtspr l2cr, r3 87a47a12beSStefan Roese sync 88a47a12beSStefan Roese1: mfspr r3, l2cr 89a47a12beSStefan Roese oris r3, r3, L2CR_L2I@h 90a47a12beSStefan Roese mtspr l2cr, r3 91a47a12beSStefan Roese 92a47a12beSStefan Roeseinvl2: 93a47a12beSStefan Roese mfspr r3, l2cr 94a47a12beSStefan Roese andis. r3, r3, L2CR_L2I@h 95a47a12beSStefan Roese bne invl2 96a47a12beSStefan Roese sync 97a47a12beSStefan Roese#endif 98a47a12beSStefan Roese 99a47a12beSStefan Roese /* enable and invalidate the data cache */ 100a47a12beSStefan Roese mfspr r3, HID0 101a47a12beSStefan Roese li r5, HID0_DCFI|HID0_DLOCK 102a47a12beSStefan Roese andc r3, r3, r5 103a47a12beSStefan Roese mtspr HID0, r3 /* no invalidate, unlock */ 104a47a12beSStefan Roese ori r3, r3, HID0_DCE 105a47a12beSStefan Roese ori r5, r3, HID0_DCFI 106a47a12beSStefan Roese mtspr HID0, r5 /* enable + invalidate */ 107a47a12beSStefan Roese mtspr HID0, r3 /* enable */ 108a47a12beSStefan Roese sync 109a47a12beSStefan Roese#ifdef CONFIG_SYS_L2 110a47a12beSStefan Roese sync 111a47a12beSStefan Roese lis r3, L2_ENABLE@h 112a47a12beSStefan Roese ori r3, r3, L2_ENABLE@l 113a47a12beSStefan Roese mtspr l2cr, r3 114a47a12beSStefan Roese isync 115a47a12beSStefan Roese sync 116a47a12beSStefan Roese#endif 117a47a12beSStefan Roese 118a47a12beSStefan Roese /* enable and invalidate the instruction cache*/ 119a47a12beSStefan Roese mfspr r3, HID0 120a47a12beSStefan Roese li r5, HID0_ICFI|HID0_ILOCK 121a47a12beSStefan Roese andc r3, r3, r5 122a47a12beSStefan Roese ori r3, r3, HID0_ICE 123a47a12beSStefan Roese ori r5, r3, HID0_ICFI 124a47a12beSStefan Roese mtspr HID0, r5 125a47a12beSStefan Roese mtspr HID0, r3 126a47a12beSStefan Roese isync 127a47a12beSStefan Roese sync 128a47a12beSStefan Roese 129a47a12beSStefan Roese /* TBEN in HID0 */ 130a47a12beSStefan Roese mfspr r4, HID0 131a47a12beSStefan Roese oris r4, r4, 0x0400 132a47a12beSStefan Roese mtspr HID0, r4 133a47a12beSStefan Roese sync 134a47a12beSStefan Roese isync 135a47a12beSStefan Roese 136a47a12beSStefan Roese /* MCP|SYNCBE|ABE in HID1 */ 137a47a12beSStefan Roese mfspr r4, HID1 138a47a12beSStefan Roese oris r4, r4, 0x8000 139a47a12beSStefan Roese ori r4, r4, 0x0C00 140a47a12beSStefan Roese mtspr HID1, r4 141a47a12beSStefan Roese sync 142a47a12beSStefan Roese isync 143a47a12beSStefan Roese 144a47a12beSStefan Roese lis r3, CONFIG_LINUX_RESET_VEC@h 145a47a12beSStefan Roese ori r3, r3, CONFIG_LINUX_RESET_VEC@l 146a47a12beSStefan Roese mtlr r3 147a47a12beSStefan Roese blr 148a47a12beSStefan Roese 149a47a12beSStefan Roese /* Never Returns, Running in Linux Now */ 150