1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2a47a12beSStefan Roese /*
3689f00fcSPrabhakar Kushwaha * Copyright 2009-2012 Freescale Semiconductor, Inc
4a47a12beSStefan Roese */
5a47a12beSStefan Roese
6a47a12beSStefan Roese #include <common.h>
7a47a12beSStefan Roese #include <asm/processor.h>
8a47a12beSStefan Roese #include <asm/mmu.h>
9a47a12beSStefan Roese #include <asm/fsl_law.h>
10e8e6197aSPoonam Aggrwal #include <asm/io.h>
11a47a12beSStefan Roese
12a47a12beSStefan Roese DECLARE_GLOBAL_DATA_PTR;
13a47a12beSStefan Roese
1474fa22edSPrabhakar Kushwaha #ifdef CONFIG_A003399_NOR_WORKAROUND
setup_ifc(void)15bc6bbd6bSPoonam Aggrwal void setup_ifc(void)
16bc6bbd6bSPoonam Aggrwal {
1739b0bbbbSJaiprakash Singh struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
18bc6bbd6bSPoonam Aggrwal u32 _mas0, _mas1, _mas2, _mas3, _mas7;
19bc6bbd6bSPoonam Aggrwal phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
20bc6bbd6bSPoonam Aggrwal
21bc6bbd6bSPoonam Aggrwal /*
22bc6bbd6bSPoonam Aggrwal * Adjust the TLB we were running out of to match the phys addr of the
23bc6bbd6bSPoonam Aggrwal * chip select we are adjusting and will return to.
24bc6bbd6bSPoonam Aggrwal */
25bc6bbd6bSPoonam Aggrwal flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
26bc6bbd6bSPoonam Aggrwal
27bc6bbd6bSPoonam Aggrwal _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
28bc6bbd6bSPoonam Aggrwal _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
29bc6bbd6bSPoonam Aggrwal MAS1_TSIZE(BOOKE_PAGESZ_4M);
30bc6bbd6bSPoonam Aggrwal _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
31bc6bbd6bSPoonam Aggrwal _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
32bc6bbd6bSPoonam Aggrwal _mas7 = FSL_BOOKE_MAS7(flash_phys);
33bc6bbd6bSPoonam Aggrwal
34bc6bbd6bSPoonam Aggrwal mtspr(MAS0, _mas0);
35bc6bbd6bSPoonam Aggrwal mtspr(MAS1, _mas1);
36bc6bbd6bSPoonam Aggrwal mtspr(MAS2, _mas2);
37bc6bbd6bSPoonam Aggrwal mtspr(MAS3, _mas3);
38bc6bbd6bSPoonam Aggrwal mtspr(MAS7, _mas7);
39bc6bbd6bSPoonam Aggrwal
40bc6bbd6bSPoonam Aggrwal asm volatile("isync;msync;tlbwe;isync");
41bc6bbd6bSPoonam Aggrwal
42689f00fcSPrabhakar Kushwaha #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
43689f00fcSPrabhakar Kushwaha /*
44689f00fcSPrabhakar Kushwaha * TLB entry for debuggging in AS1
45689f00fcSPrabhakar Kushwaha * Create temporary TLB entry in AS0 to handle debug exception
46689f00fcSPrabhakar Kushwaha * As on debug exception MSR is cleared i.e. Address space is changed
47689f00fcSPrabhakar Kushwaha * to 0. A TLB entry (in AS0) is required to handle debug exception generated
48689f00fcSPrabhakar Kushwaha * in AS1.
49689f00fcSPrabhakar Kushwaha *
50689f00fcSPrabhakar Kushwaha * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
51689f00fcSPrabhakar Kushwaha * bacause flash's physical address is going to change as
52689f00fcSPrabhakar Kushwaha * CONFIG_SYS_FLASH_BASE_PHYS.
53689f00fcSPrabhakar Kushwaha */
54689f00fcSPrabhakar Kushwaha _mas0 = MAS0_TLBSEL(1) |
55689f00fcSPrabhakar Kushwaha MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
56689f00fcSPrabhakar Kushwaha _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT |
57689f00fcSPrabhakar Kushwaha MAS1_TSIZE(BOOKE_PAGESZ_4M);
58689f00fcSPrabhakar Kushwaha _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
59689f00fcSPrabhakar Kushwaha _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
60689f00fcSPrabhakar Kushwaha _mas7 = FSL_BOOKE_MAS7(flash_phys);
61689f00fcSPrabhakar Kushwaha
62689f00fcSPrabhakar Kushwaha mtspr(MAS0, _mas0);
63689f00fcSPrabhakar Kushwaha mtspr(MAS1, _mas1);
64689f00fcSPrabhakar Kushwaha mtspr(MAS2, _mas2);
65689f00fcSPrabhakar Kushwaha mtspr(MAS3, _mas3);
66689f00fcSPrabhakar Kushwaha mtspr(MAS7, _mas7);
67689f00fcSPrabhakar Kushwaha
68689f00fcSPrabhakar Kushwaha asm volatile("isync;msync;tlbwe;isync");
69689f00fcSPrabhakar Kushwaha #endif
70689f00fcSPrabhakar Kushwaha
71689f00fcSPrabhakar Kushwaha /* Change flash's physical address */
7239b0bbbbSJaiprakash Singh ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
7339b0bbbbSJaiprakash Singh ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
7439b0bbbbSJaiprakash Singh ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
75bc6bbd6bSPoonam Aggrwal
76bc6bbd6bSPoonam Aggrwal return ;
77bc6bbd6bSPoonam Aggrwal }
78bc6bbd6bSPoonam Aggrwal #endif
79bc6bbd6bSPoonam Aggrwal
80a47a12beSStefan Roese /* We run cpu_init_early_f in AS = 1 */
cpu_init_early_f(void * fdt)81fa08d395SAlexander Graf void cpu_init_early_f(void *fdt)
82a47a12beSStefan Roese {
83a47a12beSStefan Roese u32 mas0, mas1, mas2, mas3, mas7;
84fb855f43SPoonam Aggrwal #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
85fb855f43SPoonam Aggrwal ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
86fb855f43SPoonam Aggrwal #endif
8774fa22edSPrabhakar Kushwaha #ifdef CONFIG_A003399_NOR_WORKAROUND
88bc6bbd6bSPoonam Aggrwal ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
89cfee584eSPoonam Aggrwal u32 *dst, *src;
90bc6bbd6bSPoonam Aggrwal void (*setup_ifc_sram)(void);
9150689461Smario.six@gdsys.cc int i;
92bc6bbd6bSPoonam Aggrwal #endif
93a47a12beSStefan Roese
94a47a12beSStefan Roese /* Pointer is writable since we allocated a register for it */
95a47a12beSStefan Roese gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
96a47a12beSStefan Roese
9750689461Smario.six@gdsys.cc /* gd area was zeroed during startup */
98a47a12beSStefan Roese
9910343403SYork Sun #ifdef CONFIG_ARCH_QEMU_E500
100fa08d395SAlexander Graf /*
101fa08d395SAlexander Graf * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
102fa08d395SAlexander Graf * so we need to populate it before it accesses it.
103fa08d395SAlexander Graf */
104fa08d395SAlexander Graf gd->fdt_blob = fdt;
10573a56b6eSYork Sun #endif
106fa08d395SAlexander Graf
107e8e6197aSPoonam Aggrwal mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
108e8e6197aSPoonam Aggrwal mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
109a47a12beSStefan Roese mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
110a47a12beSStefan Roese mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
111a47a12beSStefan Roese mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
112a47a12beSStefan Roese
113a47a12beSStefan Roese write_tlb(mas0, mas1, mas2, mas3, mas7);
114a47a12beSStefan Roese
115fb855f43SPoonam Aggrwal /*
116fb855f43SPoonam Aggrwal * Work Around for IFC Erratum A-003549. This issue is P1010
117fb855f43SPoonam Aggrwal * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
118fb855f43SPoonam Aggrwal * Hence specifically selecting CS3.
119fb855f43SPoonam Aggrwal */
120fb855f43SPoonam Aggrwal #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
121fb855f43SPoonam Aggrwal setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
122fb855f43SPoonam Aggrwal #endif
123fb855f43SPoonam Aggrwal
124a47a12beSStefan Roese init_laws();
125bc6bbd6bSPoonam Aggrwal
126bc6bbd6bSPoonam Aggrwal /*
127bc6bbd6bSPoonam Aggrwal * Work Around for IFC Erratum A003399, issue will hit only when execution
128bc6bbd6bSPoonam Aggrwal * from NOR Flash
129bc6bbd6bSPoonam Aggrwal */
13074fa22edSPrabhakar Kushwaha #ifdef CONFIG_A003399_NOR_WORKAROUND
131bc6bbd6bSPoonam Aggrwal #define SRAM_BASE_ADDR (0x00000000)
132bc6bbd6bSPoonam Aggrwal /* TLB for SRAM */
133bc6bbd6bSPoonam Aggrwal mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
134bc6bbd6bSPoonam Aggrwal mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
135bc6bbd6bSPoonam Aggrwal MAS1_TSIZE(BOOKE_PAGESZ_1M);
136bc6bbd6bSPoonam Aggrwal mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
137bc6bbd6bSPoonam Aggrwal mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR);
138bc6bbd6bSPoonam Aggrwal mas7 = FSL_BOOKE_MAS7(0);
139bc6bbd6bSPoonam Aggrwal
140bc6bbd6bSPoonam Aggrwal write_tlb(mas0, mas1, mas2, mas3, mas7);
141bc6bbd6bSPoonam Aggrwal
142bc6bbd6bSPoonam Aggrwal out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
143bc6bbd6bSPoonam Aggrwal
144bc6bbd6bSPoonam Aggrwal out_be32(&l2cache->l2errdis,
145bc6bbd6bSPoonam Aggrwal (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
146bc6bbd6bSPoonam Aggrwal
147bc6bbd6bSPoonam Aggrwal out_be32(&l2cache->l2ctl,
148bc6bbd6bSPoonam Aggrwal (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
149bc6bbd6bSPoonam Aggrwal
150bc6bbd6bSPoonam Aggrwal /*
151bc6bbd6bSPoonam Aggrwal * Copy the code in setup_ifc to L2SRAM. Do a word copy
152bc6bbd6bSPoonam Aggrwal * because NOR Flash on P1010 does not support byte
153bc6bbd6bSPoonam Aggrwal * access (Erratum IFC-A002769)
154bc6bbd6bSPoonam Aggrwal */
155bc6bbd6bSPoonam Aggrwal setup_ifc_sram = (void *)SRAM_BASE_ADDR;
156bc6bbd6bSPoonam Aggrwal dst = (u32 *) SRAM_BASE_ADDR;
157bc6bbd6bSPoonam Aggrwal src = (u32 *) setup_ifc;
1580060517aSWolfgang Denk for (i = 0; i < 1024; i++) {
1590060517aSWolfgang Denk /* cppcheck-suppress nullPointer */
160cfee584eSPoonam Aggrwal *dst++ = *src++;
1610060517aSWolfgang Denk }
162bc6bbd6bSPoonam Aggrwal
1630060517aSWolfgang Denk /* cppcheck-suppress nullPointer */
164bc6bbd6bSPoonam Aggrwal setup_ifc_sram();
165bc6bbd6bSPoonam Aggrwal
166bc6bbd6bSPoonam Aggrwal /* CLEANUP */
167bc6bbd6bSPoonam Aggrwal clrbits_be32(&l2cache->l2ctl,
168bc6bbd6bSPoonam Aggrwal (MPC85xx_L2CTL_L2E |
169bc6bbd6bSPoonam Aggrwal MPC85xx_L2CTL_L2SRAM_ENTIRE));
170bc6bbd6bSPoonam Aggrwal out_be32(&l2cache->l2srbar0, 0x0);
171bc6bbd6bSPoonam Aggrwal #endif
172bc6bbd6bSPoonam Aggrwal
173e8e6197aSPoonam Aggrwal invalidate_tlb(1);
1747065b7d4SRuchika Gupta
1752a693605SPrabhakar Kushwaha #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \
1762a693605SPrabhakar Kushwaha !(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \
1772a693605SPrabhakar Kushwaha !defined(CONFIG_NAND_SPL)
178bd7c023eSPrabhakar Kushwaha disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
179bd7c023eSPrabhakar Kushwaha #endif
180bd7c023eSPrabhakar Kushwaha
181a47a12beSStefan Roese init_tlbs();
182a47a12beSStefan Roese }
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