1*83d290c5STom Rini/* SPDX-License-Identifier: GPL-2.0+ */ 2a47a12beSStefan Roese/* 31605cc9eSBecky Bruce * Copyright 2004, 2007, 2011 Freescale Semiconductor. 4a47a12beSStefan Roese * Srikanth Srinivasan <srikanth.srinivaan@freescale.com> 5a47a12beSStefan Roese */ 6a47a12beSStefan Roese 7a47a12beSStefan Roese/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards 8a47a12beSStefan Roese * 9a47a12beSStefan Roese * 10a47a12beSStefan Roese * The processor starts at 0xfff00100 and the code is executed 11a47a12beSStefan Roese * from flash. The code is organized to be at an other address 12a47a12beSStefan Roese * in memory, but as long we don't jump around before relocating. 13a47a12beSStefan Roese * board_init lies at a quite high address and when the cpu has 14a47a12beSStefan Roese * jumped there, everything is ok. 15a47a12beSStefan Roese */ 1625ddd1fbSWolfgang Denk#include <asm-offsets.h> 17a47a12beSStefan Roese#include <config.h> 18a47a12beSStefan Roese#include <mpc86xx.h> 19a47a12beSStefan Roese#include <version.h> 20a47a12beSStefan Roese 21a47a12beSStefan Roese#include <ppc_asm.tmpl> 22a47a12beSStefan Roese#include <ppc_defs.h> 23a47a12beSStefan Roese 24a47a12beSStefan Roese#include <asm/cache.h> 25a47a12beSStefan Roese#include <asm/mmu.h> 26d98b0523SPeter Tyser#include <asm/u-boot.h> 27a47a12beSStefan Roese 28a47a12beSStefan Roese/* 29a47a12beSStefan Roese * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions 30a47a12beSStefan Roese */ 31a47a12beSStefan Roese 32a47a12beSStefan Roese/* 33a47a12beSStefan Roese * Set up GOT: Global Offset Table 34a47a12beSStefan Roese * 35a47a12beSStefan Roese * Use r12 to access the GOT 36a47a12beSStefan Roese */ 37a47a12beSStefan Roese START_GOT 38a47a12beSStefan Roese GOT_ENTRY(_GOT2_TABLE_) 39a47a12beSStefan Roese GOT_ENTRY(_FIXUP_TABLE_) 40a47a12beSStefan Roese 41a47a12beSStefan Roese GOT_ENTRY(_start) 42a47a12beSStefan Roese GOT_ENTRY(_start_of_vectors) 43a47a12beSStefan Roese GOT_ENTRY(_end_of_vectors) 44a47a12beSStefan Roese GOT_ENTRY(transfer_to_handler) 45a47a12beSStefan Roese 46a47a12beSStefan Roese GOT_ENTRY(__init_end) 473929fb0aSSimon Glass GOT_ENTRY(__bss_end) 48a47a12beSStefan Roese GOT_ENTRY(__bss_start) 49a47a12beSStefan Roese END_GOT 50a47a12beSStefan Roese 51a47a12beSStefan Roese/* 52a47a12beSStefan Roese * r3 - 1st arg to board_init(): IMMP pointer 53a47a12beSStefan Roese * r4 - 2nd arg to board_init(): boot flag 54a47a12beSStefan Roese */ 55a47a12beSStefan Roese .text 56a47a12beSStefan Roese .long 0x27051956 /* U-Boot Magic Number */ 57a47a12beSStefan Roese .globl version_string 58a47a12beSStefan Roeseversion_string: 5909c2e90cSAndreas Bießmann .ascii U_BOOT_VERSION_STRING, "\0" 60a47a12beSStefan Roese 61a47a12beSStefan Roese . = EXC_OFF_SYS_RESET 62a47a12beSStefan Roese .globl _start 63a47a12beSStefan Roese_start: 64a47a12beSStefan Roese b boot_cold 65a47a12beSStefan Roese 66a47a12beSStefan Roese /* the boot code is located below the exception table */ 67a47a12beSStefan Roese 68a47a12beSStefan Roese .globl _start_of_vectors 69a47a12beSStefan Roese_start_of_vectors: 70a47a12beSStefan Roese 71a47a12beSStefan Roese/* Machine check */ 72a47a12beSStefan Roese STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) 73a47a12beSStefan Roese 74a47a12beSStefan Roese/* Data Storage exception. */ 75a47a12beSStefan Roese STD_EXCEPTION(0x300, DataStorage, UnknownException) 76a47a12beSStefan Roese 77a47a12beSStefan Roese/* Instruction Storage exception. */ 78a47a12beSStefan Roese STD_EXCEPTION(0x400, InstStorage, UnknownException) 79a47a12beSStefan Roese 80a47a12beSStefan Roese/* External Interrupt exception. */ 81a47a12beSStefan Roese STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 82a47a12beSStefan Roese 83a47a12beSStefan Roese/* Alignment exception. */ 84a47a12beSStefan Roese . = 0x600 85a47a12beSStefan RoeseAlignment: 86a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 87a47a12beSStefan Roese mfspr r4,DAR 88a47a12beSStefan Roese stw r4,_DAR(r21) 89a47a12beSStefan Roese mfspr r5,DSISR 90a47a12beSStefan Roese stw r5,_DSISR(r21) 91a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 92a47a12beSStefan Roese EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 93a47a12beSStefan Roese 94a47a12beSStefan Roese/* Program check exception */ 95a47a12beSStefan Roese . = 0x700 96a47a12beSStefan RoeseProgramCheck: 97a47a12beSStefan Roese EXCEPTION_PROLOG(SRR0, SRR1) 98a47a12beSStefan Roese addi r3,r1,STACK_FRAME_OVERHEAD 99a47a12beSStefan Roese EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 100a47a12beSStefan Roese MSR_KERNEL, COPY_EE) 101a47a12beSStefan Roese 102a47a12beSStefan Roese STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 103a47a12beSStefan Roese 104a47a12beSStefan Roese /* I guess we could implement decrementer, and may have 105a47a12beSStefan Roese * to someday for timekeeping. 106a47a12beSStefan Roese */ 107a47a12beSStefan Roese STD_EXCEPTION(0x900, Decrementer, timer_interrupt) 108a47a12beSStefan Roese STD_EXCEPTION(0xa00, Trap_0a, UnknownException) 109a47a12beSStefan Roese STD_EXCEPTION(0xb00, Trap_0b, UnknownException) 110a47a12beSStefan Roese STD_EXCEPTION(0xc00, SystemCall, UnknownException) 111a47a12beSStefan Roese STD_EXCEPTION(0xd00, SingleStep, UnknownException) 112a47a12beSStefan Roese STD_EXCEPTION(0xe00, Trap_0e, UnknownException) 113a47a12beSStefan Roese STD_EXCEPTION(0xf00, Trap_0f, UnknownException) 114a47a12beSStefan Roese STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) 115a47a12beSStefan Roese STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) 116a47a12beSStefan Roese STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) 117a47a12beSStefan Roese STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) 118a47a12beSStefan Roese STD_EXCEPTION(0x1400, DataTLBError, UnknownException) 119a47a12beSStefan Roese STD_EXCEPTION(0x1500, Reserved5, UnknownException) 120a47a12beSStefan Roese STD_EXCEPTION(0x1600, Reserved6, UnknownException) 121a47a12beSStefan Roese STD_EXCEPTION(0x1700, Reserved7, UnknownException) 122a47a12beSStefan Roese STD_EXCEPTION(0x1800, Reserved8, UnknownException) 123a47a12beSStefan Roese STD_EXCEPTION(0x1900, Reserved9, UnknownException) 124a47a12beSStefan Roese STD_EXCEPTION(0x1a00, ReservedA, UnknownException) 125a47a12beSStefan Roese STD_EXCEPTION(0x1b00, ReservedB, UnknownException) 126a47a12beSStefan Roese STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) 127a47a12beSStefan Roese STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) 128a47a12beSStefan Roese STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) 129a47a12beSStefan Roese STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) 130a47a12beSStefan Roese 131a47a12beSStefan Roese .globl _end_of_vectors 132a47a12beSStefan Roese_end_of_vectors: 133a47a12beSStefan Roese 134a47a12beSStefan Roese . = 0x2000 135a47a12beSStefan Roese 136a47a12beSStefan Roeseboot_cold: 137a47a12beSStefan Roese /* 138a47a12beSStefan Roese * NOTE: Only Cpu 0 will ever come here. Other cores go to an 139a47a12beSStefan Roese * address specified by the BPTR 140a47a12beSStefan Roese */ 141a47a12beSStefan Roese1: 142a47a12beSStefan Roese#ifdef CONFIG_SYS_RAMBOOT 143a47a12beSStefan Roese /* disable everything */ 144a47a12beSStefan Roese li r0, 0 145a47a12beSStefan Roese mtspr HID0, r0 146a47a12beSStefan Roese sync 147a47a12beSStefan Roese mtmsr 0 148a47a12beSStefan Roese#endif 149a47a12beSStefan Roese 150a47a12beSStefan Roese /* Invalidate BATs */ 151a47a12beSStefan Roese bl invalidate_bats 152a47a12beSStefan Roese sync 153a47a12beSStefan Roese /* Invalidate all of TLB before MMU turn on */ 154a47a12beSStefan Roese bl clear_tlbs 155a47a12beSStefan Roese sync 156a47a12beSStefan Roese 157a47a12beSStefan Roese#ifdef CONFIG_SYS_L2 158a47a12beSStefan Roese /* init the L2 cache */ 159a47a12beSStefan Roese lis r3, L2_INIT@h 160a47a12beSStefan Roese ori r3, r3, L2_INIT@l 161a47a12beSStefan Roese mtspr l2cr, r3 162a47a12beSStefan Roese /* invalidate the L2 cache */ 163a47a12beSStefan Roese bl l2cache_invalidate 164a47a12beSStefan Roese sync 165a47a12beSStefan Roese#endif 166a47a12beSStefan Roese 167a47a12beSStefan Roese /* 168a47a12beSStefan Roese * Calculate absolute address in FLASH and jump there 169a47a12beSStefan Roese *------------------------------------------------------*/ 170a47a12beSStefan Roese lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h 171a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l 172a47a12beSStefan Roese addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET 173a47a12beSStefan Roese mtlr r3 174a47a12beSStefan Roese blr 175a47a12beSStefan Roese 176a47a12beSStefan Roesein_flash: 177a47a12beSStefan Roese /* let the C-code set up the rest */ 178a47a12beSStefan Roese /* */ 179a47a12beSStefan Roese /* Be careful to keep code relocatable ! */ 180a47a12beSStefan Roese /*------------------------------------------------------*/ 181a47a12beSStefan Roese /* perform low-level init */ 182a47a12beSStefan Roese 183a47a12beSStefan Roese /* enable extended addressing */ 184a47a12beSStefan Roese bl enable_ext_addr 185a47a12beSStefan Roese 186a47a12beSStefan Roese /* setup the bats */ 187a47a12beSStefan Roese bl early_bats 188a47a12beSStefan Roese 189a47a12beSStefan Roese /* 190a47a12beSStefan Roese * Cache must be enabled here for stack-in-cache trick. 191a47a12beSStefan Roese * This means we need to enable the BATS. 192a47a12beSStefan Roese * Cache should be turned on after BATs, since by default 193a47a12beSStefan Roese * everything is write-through. 194a47a12beSStefan Roese */ 195a47a12beSStefan Roese 196a47a12beSStefan Roese /* enable address translation */ 197a47a12beSStefan Roese mfmsr r5 198a47a12beSStefan Roese ori r5, r5, (MSR_IR | MSR_DR) 199a47a12beSStefan Roese lis r3,addr_trans_enabled@h 200a47a12beSStefan Roese ori r3, r3, addr_trans_enabled@l 201a47a12beSStefan Roese mtspr SPRN_SRR0,r3 202a47a12beSStefan Roese mtspr SPRN_SRR1,r5 203a47a12beSStefan Roese rfi 204a47a12beSStefan Roese 205a47a12beSStefan Roeseaddr_trans_enabled: 206a47a12beSStefan Roese /* enable and invalidate the data cache */ 207a47a12beSStefan Roese/* bl l1dcache_enable */ 208a47a12beSStefan Roese bl dcache_enable 209a47a12beSStefan Roese sync 210a47a12beSStefan Roese 211a47a12beSStefan Roese#if 1 212a47a12beSStefan Roese bl icache_enable 213a47a12beSStefan Roese#endif 214a47a12beSStefan Roese 215a47a12beSStefan Roese#ifdef CONFIG_SYS_INIT_RAM_LOCK 216a47a12beSStefan Roese bl lock_ram_in_cache 217a47a12beSStefan Roese sync 218a47a12beSStefan Roese#endif 219a47a12beSStefan Roese 220a47a12beSStefan Roese#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 221a47a12beSStefan Roese bl setup_ccsrbar 222a47a12beSStefan Roese#endif 223a47a12beSStefan Roese 224a47a12beSStefan Roese /* set up the stack pointer in our newly created 225a47a12beSStefan Roese * cache-ram (r1) */ 226a47a12beSStefan Roese lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h 227a47a12beSStefan Roese ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l 228a47a12beSStefan Roese 229a47a12beSStefan Roese li r0, 0 /* Make room for stack frame header and */ 230a47a12beSStefan Roese stwu r0, -4(r1) /* clear final stack frame so that */ 231a47a12beSStefan Roese stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 232a47a12beSStefan Roese 233a47a12beSStefan Roese GET_GOT /* initialize GOT access */ 2348c4734e9SWolfgang Denk 235a47a12beSStefan Roese /* run low-level CPU init code (from Flash) */ 236a47a12beSStefan Roese bl cpu_init_f 237a47a12beSStefan Roese sync 238a47a12beSStefan Roese 239a47a12beSStefan Roese#ifdef RUN_DIAG 240a47a12beSStefan Roese 241a47a12beSStefan Roese /* Load PX_AUX register address in r4 */ 242a47a12beSStefan Roese lis r4, PIXIS_BASE@h 243a47a12beSStefan Roese ori r4, r4, 0x6 244a47a12beSStefan Roese /* Load contents of PX_AUX in r3 bits 24 to 31*/ 245a47a12beSStefan Roese lbz r3, 0(r4) 246a47a12beSStefan Roese 247a47a12beSStefan Roese /* Mask and obtain the bit in r3 */ 248a47a12beSStefan Roese rlwinm. r3, r3, 0, 24, 24 249a47a12beSStefan Roese /* If not zero, jump and continue with u-boot */ 250a47a12beSStefan Roese bne diag_done 251a47a12beSStefan Roese 252a47a12beSStefan Roese /* Load back contents of PX_AUX in r3 bits 24 to 31 */ 253a47a12beSStefan Roese lbz r3, 0(r4) 254a47a12beSStefan Roese /* Set the MSB of the register value */ 255a47a12beSStefan Roese ori r3, r3, 0x80 256a47a12beSStefan Roese /* Write value in r3 back to PX_AUX */ 257a47a12beSStefan Roese stb r3, 0(r4) 258a47a12beSStefan Roese 259a47a12beSStefan Roese /* Get the address to jump to in r3*/ 260a47a12beSStefan Roese lis r3, CONFIG_SYS_DIAG_ADDR@h 261a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DIAG_ADDR@l 262a47a12beSStefan Roese 263a47a12beSStefan Roese /* Load the LR with the branch address */ 264a47a12beSStefan Roese mtlr r3 265a47a12beSStefan Roese 266a47a12beSStefan Roese /* Branch to diagnostic */ 267a47a12beSStefan Roese blr 268a47a12beSStefan Roese 269a47a12beSStefan Roesediag_done: 270a47a12beSStefan Roese#endif 271a47a12beSStefan Roese 272a47a12beSStefan Roese/* bl l2cache_enable */ 273a47a12beSStefan Roese 274a47a12beSStefan Roese /* run 1st part of board init code (from Flash) */ 2758bae330fSYork Sun li r3, 0 /* clear boot_flag for calling board_init_f */ 276a47a12beSStefan Roese bl board_init_f 277a47a12beSStefan Roese sync 278a47a12beSStefan Roese 27952ebd9c1SPeter Tyser /* NOTREACHED - board_init_f() does not return */ 280a47a12beSStefan Roese 281a47a12beSStefan Roese .globl invalidate_bats 282a47a12beSStefan Roeseinvalidate_bats: 283a47a12beSStefan Roese 284a47a12beSStefan Roese li r0, 0 285a47a12beSStefan Roese /* invalidate BATs */ 286a47a12beSStefan Roese mtspr IBAT0U, r0 287a47a12beSStefan Roese mtspr IBAT1U, r0 288a47a12beSStefan Roese mtspr IBAT2U, r0 289a47a12beSStefan Roese mtspr IBAT3U, r0 290a47a12beSStefan Roese mtspr IBAT4U, r0 291a47a12beSStefan Roese mtspr IBAT5U, r0 292a47a12beSStefan Roese mtspr IBAT6U, r0 293a47a12beSStefan Roese mtspr IBAT7U, r0 294a47a12beSStefan Roese 295a47a12beSStefan Roese isync 296a47a12beSStefan Roese mtspr DBAT0U, r0 297a47a12beSStefan Roese mtspr DBAT1U, r0 298a47a12beSStefan Roese mtspr DBAT2U, r0 299a47a12beSStefan Roese mtspr DBAT3U, r0 300a47a12beSStefan Roese mtspr DBAT4U, r0 301a47a12beSStefan Roese mtspr DBAT5U, r0 302a47a12beSStefan Roese mtspr DBAT6U, r0 303a47a12beSStefan Roese mtspr DBAT7U, r0 304a47a12beSStefan Roese 305a47a12beSStefan Roese isync 306a47a12beSStefan Roese sync 307a47a12beSStefan Roese blr 308a47a12beSStefan Roese 3091605cc9eSBecky Bruce#define CONFIG_BAT_PAIR(n) \ 3101605cc9eSBecky Bruce lis r4, CONFIG_SYS_IBAT##n##L@h; \ 3111605cc9eSBecky Bruce ori r4, r4, CONFIG_SYS_IBAT##n##L@l; \ 3121605cc9eSBecky Bruce lis r3, CONFIG_SYS_IBAT##n##U@h; \ 3131605cc9eSBecky Bruce ori r3, r3, CONFIG_SYS_IBAT##n##U@l; \ 3141605cc9eSBecky Bruce mtspr IBAT##n##L, r4; \ 3151605cc9eSBecky Bruce mtspr IBAT##n##U, r3; \ 3161605cc9eSBecky Bruce lis r4, CONFIG_SYS_DBAT##n##L@h; \ 3171605cc9eSBecky Bruce ori r4, r4, CONFIG_SYS_DBAT##n##L@l; \ 3181605cc9eSBecky Bruce lis r3, CONFIG_SYS_DBAT##n##U@h; \ 3191605cc9eSBecky Bruce ori r3, r3, CONFIG_SYS_DBAT##n##U@l; \ 3201605cc9eSBecky Bruce mtspr DBAT##n##L, r4; \ 3211605cc9eSBecky Bruce mtspr DBAT##n##U, r3; 3221605cc9eSBecky Bruce 3231605cc9eSBecky Bruce/* 3241605cc9eSBecky Bruce * setup_bats: 3251605cc9eSBecky Bruce * 3261605cc9eSBecky Bruce * Set up the final BAT registers now that setup is done. 3271605cc9eSBecky Bruce * 3281605cc9eSBecky Bruce * Assumes that: 3291605cc9eSBecky Bruce * 1) Address translation is enabled upon entry 3301605cc9eSBecky Bruce * 2) The boot rom is still accessible via 1:1 translation 3311605cc9eSBecky Bruce */ 3321605cc9eSBecky Bruce .globl setup_bats 3331605cc9eSBecky Brucesetup_bats: 3341605cc9eSBecky Bruce mflr r5 3351605cc9eSBecky Bruce sync 3361605cc9eSBecky Bruce 3371605cc9eSBecky Bruce /* 3381605cc9eSBecky Bruce * When we disable address translation, we will get 1:1 (VA==PA) 3391605cc9eSBecky Bruce * translation. The only place we know for sure is safe for that is 3401605cc9eSBecky Bruce * the bootrom where we originally started out. Pop back into there. 3411605cc9eSBecky Bruce */ 3421605cc9eSBecky Bruce lis r4, CONFIG_SYS_MONITOR_BASE_EARLY@h 3431605cc9eSBecky Bruce ori r4, r4, CONFIG_SYS_MONITOR_BASE_EARLY@l 3441605cc9eSBecky Bruce addi r4, r4, trans_disabled - _start + EXC_OFF_SYS_RESET 3451605cc9eSBecky Bruce 3461605cc9eSBecky Bruce /* disable address translation */ 3471605cc9eSBecky Bruce mfmsr r3 3481605cc9eSBecky Bruce rlwinm r3, r3, 0, 28, 25 3491605cc9eSBecky Bruce mtspr SRR0, r4 3501605cc9eSBecky Bruce mtspr SRR1, r3 3511605cc9eSBecky Bruce rfi 3521605cc9eSBecky Bruce 3531605cc9eSBecky Brucetrans_disabled: 3541605cc9eSBecky Bruce#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) \ 3551605cc9eSBecky Bruce && defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L) 3561605cc9eSBecky Bruce CONFIG_BAT_PAIR(0) 3571605cc9eSBecky Bruce#endif 3581605cc9eSBecky Bruce CONFIG_BAT_PAIR(1) 3591605cc9eSBecky Bruce CONFIG_BAT_PAIR(2) 3601605cc9eSBecky Bruce CONFIG_BAT_PAIR(3) 3611605cc9eSBecky Bruce CONFIG_BAT_PAIR(4) 3621605cc9eSBecky Bruce CONFIG_BAT_PAIR(5) 3631605cc9eSBecky Bruce CONFIG_BAT_PAIR(6) 3641605cc9eSBecky Bruce CONFIG_BAT_PAIR(7) 3651605cc9eSBecky Bruce 3661605cc9eSBecky Bruce sync 3671605cc9eSBecky Bruce isync 3681605cc9eSBecky Bruce 3691605cc9eSBecky Bruce /* Turn translation back on and return */ 3701605cc9eSBecky Bruce mfmsr r3 3711605cc9eSBecky Bruce ori r3, r3, (MSR_IR | MSR_DR) 3721605cc9eSBecky Bruce mtspr SPRN_SRR0,r5 3731605cc9eSBecky Bruce mtspr SPRN_SRR1,r3 3741605cc9eSBecky Bruce rfi 3751605cc9eSBecky Bruce 376a47a12beSStefan Roese/* 377a47a12beSStefan Roese * early_bats: 378a47a12beSStefan Roese * 379a47a12beSStefan Roese * Set up bats needed early on - this is usually the BAT for the 380a47a12beSStefan Roese * stack-in-cache, the Flash, and CCSR space 381a47a12beSStefan Roese */ 382a47a12beSStefan Roese .globl early_bats 383a47a12beSStefan Roeseearly_bats: 384a47a12beSStefan Roese /* IBAT 3 */ 385a47a12beSStefan Roese lis r4, CONFIG_SYS_IBAT3L@h 386a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT3L@l 387a47a12beSStefan Roese lis r3, CONFIG_SYS_IBAT3U@h 388a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT3U@l 389a47a12beSStefan Roese mtspr IBAT3L, r4 390a47a12beSStefan Roese mtspr IBAT3U, r3 391a47a12beSStefan Roese isync 392a47a12beSStefan Roese 393a47a12beSStefan Roese /* DBAT 3 */ 394a47a12beSStefan Roese lis r4, CONFIG_SYS_DBAT3L@h 395a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT3L@l 396a47a12beSStefan Roese lis r3, CONFIG_SYS_DBAT3U@h 397a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT3U@l 398a47a12beSStefan Roese mtspr DBAT3L, r4 399a47a12beSStefan Roese mtspr DBAT3U, r3 400a47a12beSStefan Roese isync 401a47a12beSStefan Roese 402a47a12beSStefan Roese /* IBAT 5 */ 403a47a12beSStefan Roese lis r4, CONFIG_SYS_IBAT5L@h 404a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT5L@l 405a47a12beSStefan Roese lis r3, CONFIG_SYS_IBAT5U@h 406a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT5U@l 407a47a12beSStefan Roese mtspr IBAT5L, r4 408a47a12beSStefan Roese mtspr IBAT5U, r3 409a47a12beSStefan Roese isync 410a47a12beSStefan Roese 411a47a12beSStefan Roese /* DBAT 5 */ 412a47a12beSStefan Roese lis r4, CONFIG_SYS_DBAT5L@h 413a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT5L@l 414a47a12beSStefan Roese lis r3, CONFIG_SYS_DBAT5U@h 415a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT5U@l 416a47a12beSStefan Roese mtspr DBAT5L, r4 417a47a12beSStefan Roese mtspr DBAT5U, r3 418a47a12beSStefan Roese isync 419a47a12beSStefan Roese 420a47a12beSStefan Roese /* IBAT 6 */ 421a47a12beSStefan Roese lis r4, CONFIG_SYS_IBAT6L_EARLY@h 422a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l 423a47a12beSStefan Roese lis r3, CONFIG_SYS_IBAT6U_EARLY@h 424a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l 425a47a12beSStefan Roese mtspr IBAT6L, r4 426a47a12beSStefan Roese mtspr IBAT6U, r3 427a47a12beSStefan Roese isync 428a47a12beSStefan Roese 429a47a12beSStefan Roese /* DBAT 6 */ 430a47a12beSStefan Roese lis r4, CONFIG_SYS_DBAT6L_EARLY@h 431a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l 432a47a12beSStefan Roese lis r3, CONFIG_SYS_DBAT6U_EARLY@h 433a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l 434a47a12beSStefan Roese mtspr DBAT6L, r4 435a47a12beSStefan Roese mtspr DBAT6U, r3 436a47a12beSStefan Roese isync 437a47a12beSStefan Roese 438a47a12beSStefan Roese#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 439a47a12beSStefan Roese /* IBAT 7 */ 440a47a12beSStefan Roese lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h 441a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l 442a47a12beSStefan Roese lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h 443a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l 444a47a12beSStefan Roese mtspr IBAT7L, r4 445a47a12beSStefan Roese mtspr IBAT7U, r3 446a47a12beSStefan Roese isync 447a47a12beSStefan Roese 448a47a12beSStefan Roese /* DBAT 7 */ 449a47a12beSStefan Roese lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h 450a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l 451a47a12beSStefan Roese lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h 452a47a12beSStefan Roese ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l 453a47a12beSStefan Roese mtspr DBAT7L, r4 454a47a12beSStefan Roese mtspr DBAT7U, r3 455a47a12beSStefan Roese isync 456a47a12beSStefan Roese#endif 457a47a12beSStefan Roese blr 458a47a12beSStefan Roese 459a47a12beSStefan Roese .globl clear_tlbs 460a47a12beSStefan Roeseclear_tlbs: 461a47a12beSStefan Roese addis r3, 0, 0x0000 462a47a12beSStefan Roese addis r5, 0, 0x4 463a47a12beSStefan Roese isync 464a47a12beSStefan Roesetlblp: 465a47a12beSStefan Roese tlbie r3 466a47a12beSStefan Roese sync 467a47a12beSStefan Roese addi r3, r3, 0x1000 468a47a12beSStefan Roese cmp 0, 0, r3, r5 469a47a12beSStefan Roese blt tlblp 470a47a12beSStefan Roese blr 471a47a12beSStefan Roese 472a47a12beSStefan Roese .globl disable_addr_trans 473a47a12beSStefan Roesedisable_addr_trans: 474a47a12beSStefan Roese /* disable address translation */ 475a47a12beSStefan Roese mflr r4 476a47a12beSStefan Roese mfmsr r3 477a47a12beSStefan Roese andi. r0, r3, (MSR_IR | MSR_DR) 478a47a12beSStefan Roese beqlr 479a47a12beSStefan Roese andc r3, r3, r0 480a47a12beSStefan Roese mtspr SRR0, r4 481a47a12beSStefan Roese mtspr SRR1, r3 482a47a12beSStefan Roese rfi 483a47a12beSStefan Roese 484a47a12beSStefan Roese/* 485a47a12beSStefan Roese * This code finishes saving the registers to the exception frame 486a47a12beSStefan Roese * and jumps to the appropriate handler for the exception. 487a47a12beSStefan Roese * Register r21 is pointer into trap frame, r1 has new stack pointer. 488a47a12beSStefan Roese */ 489a47a12beSStefan Roese .globl transfer_to_handler 490a47a12beSStefan Roesetransfer_to_handler: 491a47a12beSStefan Roese stw r22,_NIP(r21) 492a47a12beSStefan Roese lis r22,MSR_POW@h 493a47a12beSStefan Roese andc r23,r23,r22 494a47a12beSStefan Roese stw r23,_MSR(r21) 495a47a12beSStefan Roese SAVE_GPR(7, r21) 496a47a12beSStefan Roese SAVE_4GPRS(8, r21) 497a47a12beSStefan Roese SAVE_8GPRS(12, r21) 498a47a12beSStefan Roese SAVE_8GPRS(24, r21) 499a47a12beSStefan Roese mflr r23 500a47a12beSStefan Roese andi. r24,r23,0x3f00 /* get vector offset */ 501a47a12beSStefan Roese stw r24,TRAP(r21) 502a47a12beSStefan Roese li r22,0 503a47a12beSStefan Roese stw r22,RESULT(r21) 504a47a12beSStefan Roese mtspr SPRG2,r22 /* r1 is now kernel sp */ 505a47a12beSStefan Roese lwz r24,0(r23) /* virtual address of handler */ 506a47a12beSStefan Roese lwz r23,4(r23) /* where to go when done */ 507a47a12beSStefan Roese mtspr SRR0,r24 508a47a12beSStefan Roese mtspr SRR1,r20 509a47a12beSStefan Roese mtlr r23 510a47a12beSStefan Roese SYNC 511a47a12beSStefan Roese rfi /* jump to handler, enable MMU */ 512a47a12beSStefan Roese 513a47a12beSStefan Roeseint_return: 514a47a12beSStefan Roese mfmsr r28 /* Disable interrupts */ 515a47a12beSStefan Roese li r4,0 516a47a12beSStefan Roese ori r4,r4,MSR_EE 517a47a12beSStefan Roese andc r28,r28,r4 518a47a12beSStefan Roese SYNC /* Some chip revs need this... */ 519a47a12beSStefan Roese mtmsr r28 520a47a12beSStefan Roese SYNC 521a47a12beSStefan Roese lwz r2,_CTR(r1) 522a47a12beSStefan Roese lwz r0,_LINK(r1) 523a47a12beSStefan Roese mtctr r2 524a47a12beSStefan Roese mtlr r0 525a47a12beSStefan Roese lwz r2,_XER(r1) 526a47a12beSStefan Roese lwz r0,_CCR(r1) 527a47a12beSStefan Roese mtspr XER,r2 528a47a12beSStefan Roese mtcrf 0xFF,r0 529a47a12beSStefan Roese REST_10GPRS(3, r1) 530a47a12beSStefan Roese REST_10GPRS(13, r1) 531a47a12beSStefan Roese REST_8GPRS(23, r1) 532a47a12beSStefan Roese REST_GPR(31, r1) 533a47a12beSStefan Roese lwz r2,_NIP(r1) /* Restore environment */ 534a47a12beSStefan Roese lwz r0,_MSR(r1) 535a47a12beSStefan Roese mtspr SRR0,r2 536a47a12beSStefan Roese mtspr SRR1,r0 537a47a12beSStefan Roese lwz r0,GPR0(r1) 538a47a12beSStefan Roese lwz r2,GPR2(r1) 539a47a12beSStefan Roese lwz r1,GPR1(r1) 540a47a12beSStefan Roese SYNC 541a47a12beSStefan Roese rfi 542a47a12beSStefan Roese 543a47a12beSStefan Roese .globl dc_read 544a47a12beSStefan Roesedc_read: 545a47a12beSStefan Roese blr 546a47a12beSStefan Roese 547a47a12beSStefan Roese 548a47a12beSStefan Roese/* 549a47a12beSStefan Roese * Function: in8 550a47a12beSStefan Roese * Description: Input 8 bits 551a47a12beSStefan Roese */ 552a47a12beSStefan Roese .globl in8 553a47a12beSStefan Roesein8: 554a47a12beSStefan Roese lbz r3,0x0000(r3) 555a47a12beSStefan Roese blr 556a47a12beSStefan Roese 557a47a12beSStefan Roese/* 558a47a12beSStefan Roese * Function: out8 559a47a12beSStefan Roese * Description: Output 8 bits 560a47a12beSStefan Roese */ 561a47a12beSStefan Roese .globl out8 562a47a12beSStefan Roeseout8: 563a47a12beSStefan Roese stb r4,0x0000(r3) 564a47a12beSStefan Roese blr 565a47a12beSStefan Roese 566a47a12beSStefan Roese/* 567a47a12beSStefan Roese * Function: out16 568a47a12beSStefan Roese * Description: Output 16 bits 569a47a12beSStefan Roese */ 570a47a12beSStefan Roese .globl out16 571a47a12beSStefan Roeseout16: 572a47a12beSStefan Roese sth r4,0x0000(r3) 573a47a12beSStefan Roese blr 574a47a12beSStefan Roese 575a47a12beSStefan Roese/* 576a47a12beSStefan Roese * Function: out16r 577a47a12beSStefan Roese * Description: Byte reverse and output 16 bits 578a47a12beSStefan Roese */ 579a47a12beSStefan Roese .globl out16r 580a47a12beSStefan Roeseout16r: 581a47a12beSStefan Roese sthbrx r4,r0,r3 582a47a12beSStefan Roese blr 583a47a12beSStefan Roese 584a47a12beSStefan Roese/* 585a47a12beSStefan Roese * Function: out32 586a47a12beSStefan Roese * Description: Output 32 bits 587a47a12beSStefan Roese */ 588a47a12beSStefan Roese .globl out32 589a47a12beSStefan Roeseout32: 590a47a12beSStefan Roese stw r4,0x0000(r3) 591a47a12beSStefan Roese blr 592a47a12beSStefan Roese 593a47a12beSStefan Roese/* 594a47a12beSStefan Roese * Function: out32r 595a47a12beSStefan Roese * Description: Byte reverse and output 32 bits 596a47a12beSStefan Roese */ 597a47a12beSStefan Roese .globl out32r 598a47a12beSStefan Roeseout32r: 599a47a12beSStefan Roese stwbrx r4,r0,r3 600a47a12beSStefan Roese blr 601a47a12beSStefan Roese 602a47a12beSStefan Roese/* 603a47a12beSStefan Roese * Function: in16 604a47a12beSStefan Roese * Description: Input 16 bits 605a47a12beSStefan Roese */ 606a47a12beSStefan Roese .globl in16 607a47a12beSStefan Roesein16: 608a47a12beSStefan Roese lhz r3,0x0000(r3) 609a47a12beSStefan Roese blr 610a47a12beSStefan Roese 611a47a12beSStefan Roese/* 612a47a12beSStefan Roese * Function: in16r 613a47a12beSStefan Roese * Description: Input 16 bits and byte reverse 614a47a12beSStefan Roese */ 615a47a12beSStefan Roese .globl in16r 616a47a12beSStefan Roesein16r: 617a47a12beSStefan Roese lhbrx r3,r0,r3 618a47a12beSStefan Roese blr 619a47a12beSStefan Roese 620a47a12beSStefan Roese/* 621a47a12beSStefan Roese * Function: in32 622a47a12beSStefan Roese * Description: Input 32 bits 623a47a12beSStefan Roese */ 624a47a12beSStefan Roese .globl in32 625a47a12beSStefan Roesein32: 626a47a12beSStefan Roese lwz 3,0x0000(3) 627a47a12beSStefan Roese blr 628a47a12beSStefan Roese 629a47a12beSStefan Roese/* 630a47a12beSStefan Roese * Function: in32r 631a47a12beSStefan Roese * Description: Input 32 bits and byte reverse 632a47a12beSStefan Roese */ 633a47a12beSStefan Roese .globl in32r 634a47a12beSStefan Roesein32r: 635a47a12beSStefan Roese lwbrx r3,r0,r3 636a47a12beSStefan Roese blr 637a47a12beSStefan Roese 638a47a12beSStefan Roese/* 639a47a12beSStefan Roese * void relocate_code (addr_sp, gd, addr_moni) 640a47a12beSStefan Roese * 641a47a12beSStefan Roese * This "function" does not return, instead it continues in RAM 642a47a12beSStefan Roese * after relocating the monitor code. 643a47a12beSStefan Roese * 644a47a12beSStefan Roese * r3 = dest 645a47a12beSStefan Roese * r4 = src 646a47a12beSStefan Roese * r5 = length in bytes 647a47a12beSStefan Roese * r6 = cachelinesize 648a47a12beSStefan Roese */ 649a47a12beSStefan Roese .globl relocate_code 650a47a12beSStefan Roeserelocate_code: 651a47a12beSStefan Roese 652a47a12beSStefan Roese mr r1, r3 /* Set new stack pointer */ 653a47a12beSStefan Roese mr r9, r4 /* Save copy of Global Data pointer */ 654a47a12beSStefan Roese mr r10, r5 /* Save copy of Destination Address */ 655a47a12beSStefan Roese 656a47a12beSStefan Roese GET_GOT 657a47a12beSStefan Roese mr r3, r5 /* Destination Address */ 658a47a12beSStefan Roese lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 659a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 660a47a12beSStefan Roese lwz r5, GOT(__init_end) 661a47a12beSStefan Roese sub r5, r5, r4 662a47a12beSStefan Roese li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ 663a47a12beSStefan Roese 664a47a12beSStefan Roese /* 665a47a12beSStefan Roese * Fix GOT pointer: 666a47a12beSStefan Roese * 667a47a12beSStefan Roese * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 668a47a12beSStefan Roese * 669a47a12beSStefan Roese * Offset: 670a47a12beSStefan Roese */ 671a47a12beSStefan Roese sub r15, r10, r4 672a47a12beSStefan Roese 673a47a12beSStefan Roese /* First our own GOT */ 674a47a12beSStefan Roese add r12, r12, r15 675a47a12beSStefan Roese /* then the one used by the C code */ 676a47a12beSStefan Roese add r30, r30, r15 677a47a12beSStefan Roese 678a47a12beSStefan Roese /* 679a47a12beSStefan Roese * Now relocate code 680a47a12beSStefan Roese */ 681a47a12beSStefan Roese cmplw cr1,r3,r4 682a47a12beSStefan Roese addi r0,r5,3 683a47a12beSStefan Roese srwi. r0,r0,2 684a47a12beSStefan Roese beq cr1,4f /* In place copy is not necessary */ 685a47a12beSStefan Roese beq 7f /* Protect against 0 count */ 686a47a12beSStefan Roese mtctr r0 687a47a12beSStefan Roese bge cr1,2f 688a47a12beSStefan Roese 689a47a12beSStefan Roese la r8,-4(r4) 690a47a12beSStefan Roese la r7,-4(r3) 691a47a12beSStefan Roese1: lwzu r0,4(r8) 692a47a12beSStefan Roese stwu r0,4(r7) 693a47a12beSStefan Roese bdnz 1b 694a47a12beSStefan Roese b 4f 695a47a12beSStefan Roese 696a47a12beSStefan Roese2: slwi r0,r0,2 697a47a12beSStefan Roese add r8,r4,r0 698a47a12beSStefan Roese add r7,r3,r0 699a47a12beSStefan Roese3: lwzu r0,-4(r8) 700a47a12beSStefan Roese stwu r0,-4(r7) 701a47a12beSStefan Roese bdnz 3b 702a47a12beSStefan Roese/* 703a47a12beSStefan Roese * Now flush the cache: note that we must start from a cache aligned 704a47a12beSStefan Roese * address. Otherwise we might miss one cache line. 705a47a12beSStefan Roese */ 706a47a12beSStefan Roese4: cmpwi r6,0 707a47a12beSStefan Roese add r5,r3,r5 708a47a12beSStefan Roese beq 7f /* Always flush prefetch queue in any case */ 709a47a12beSStefan Roese subi r0,r6,1 710a47a12beSStefan Roese andc r3,r3,r0 711a47a12beSStefan Roese mr r4,r3 712a47a12beSStefan Roese5: dcbst 0,r4 713a47a12beSStefan Roese add r4,r4,r6 714a47a12beSStefan Roese cmplw r4,r5 715a47a12beSStefan Roese blt 5b 716a47a12beSStefan Roese sync /* Wait for all dcbst to complete on bus */ 717a47a12beSStefan Roese mr r4,r3 718a47a12beSStefan Roese6: icbi 0,r4 719a47a12beSStefan Roese add r4,r4,r6 720a47a12beSStefan Roese cmplw r4,r5 721a47a12beSStefan Roese blt 6b 722a47a12beSStefan Roese7: sync /* Wait for all icbi to complete on bus */ 723a47a12beSStefan Roese isync 724a47a12beSStefan Roese 725a47a12beSStefan Roese/* 726a47a12beSStefan Roese * We are done. Do not return, instead branch to second part of board 727a47a12beSStefan Roese * initialization, now running from RAM. 728a47a12beSStefan Roese */ 729a47a12beSStefan Roese addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET 730a47a12beSStefan Roese mtlr r0 731a47a12beSStefan Roese blr 732a47a12beSStefan Roese 733a47a12beSStefan Roesein_ram: 734a47a12beSStefan Roese /* 735a47a12beSStefan Roese * Relocation Function, r12 point to got2+0x8000 736a47a12beSStefan Roese * 737a47a12beSStefan Roese * Adjust got2 pointers, no need to check for 0, this code 738a47a12beSStefan Roese * already puts a few entries in the table. 739a47a12beSStefan Roese */ 740a47a12beSStefan Roese li r0,__got2_entries@sectoff@l 741a47a12beSStefan Roese la r3,GOT(_GOT2_TABLE_) 742a47a12beSStefan Roese lwz r11,GOT(_GOT2_TABLE_) 743a47a12beSStefan Roese mtctr r0 744a47a12beSStefan Roese sub r11,r3,r11 745a47a12beSStefan Roese addi r3,r3,-4 746a47a12beSStefan Roese1: lwzu r0,4(r3) 747a47a12beSStefan Roese cmpwi r0,0 748a47a12beSStefan Roese beq- 2f 749a47a12beSStefan Roese add r0,r0,r11 750a47a12beSStefan Roese stw r0,0(r3) 751a47a12beSStefan Roese2: bdnz 1b 752a47a12beSStefan Roese 753a47a12beSStefan Roese /* 754a47a12beSStefan Roese * Now adjust the fixups and the pointers to the fixups 755a47a12beSStefan Roese * in case we need to move ourselves again. 756a47a12beSStefan Roese */ 757a47a12beSStefan Roese li r0,__fixup_entries@sectoff@l 758a47a12beSStefan Roese lwz r3,GOT(_FIXUP_TABLE_) 759a47a12beSStefan Roese cmpwi r0,0 760a47a12beSStefan Roese mtctr r0 761a47a12beSStefan Roese addi r3,r3,-4 762a47a12beSStefan Roese beq 4f 763a47a12beSStefan Roese3: lwzu r4,4(r3) 764a47a12beSStefan Roese lwzux r0,r4,r11 765d1e0b10aSJoakim Tjernlund cmpwi r0,0 766a47a12beSStefan Roese add r0,r0,r11 76734bbf618SJoakim Tjernlund stw r4,0(r3) 768d1e0b10aSJoakim Tjernlund beq- 5f 769a47a12beSStefan Roese stw r0,0(r4) 770d1e0b10aSJoakim Tjernlund5: bdnz 3b 771a47a12beSStefan Roese4: 772a47a12beSStefan Roese/* clear_bss: */ 773a47a12beSStefan Roese /* 774a47a12beSStefan Roese * Now clear BSS segment 775a47a12beSStefan Roese */ 776a47a12beSStefan Roese lwz r3,GOT(__bss_start) 7773929fb0aSSimon Glass lwz r4,GOT(__bss_end) 778a47a12beSStefan Roese 779a47a12beSStefan Roese cmplw 0, r3, r4 780a47a12beSStefan Roese beq 6f 781a47a12beSStefan Roese 782a47a12beSStefan Roese li r0, 0 783a47a12beSStefan Roese5: 784a47a12beSStefan Roese stw r0, 0(r3) 785a47a12beSStefan Roese addi r3, r3, 4 786a47a12beSStefan Roese cmplw 0, r3, r4 787a47a12beSStefan Roese bne 5b 788a47a12beSStefan Roese6: 789a47a12beSStefan Roese mr r3, r9 /* Init Date pointer */ 790a47a12beSStefan Roese mr r4, r10 /* Destination Address */ 791a47a12beSStefan Roese bl board_init_r 792a47a12beSStefan Roese 793a47a12beSStefan Roese /* not reached - end relocate_code */ 794a47a12beSStefan Roese/*-----------------------------------------------------------------------*/ 795a47a12beSStefan Roese 796a47a12beSStefan Roese /* 797a47a12beSStefan Roese * Copy exception vector code to low memory 798a47a12beSStefan Roese * 799a47a12beSStefan Roese * r3: dest_addr 800a47a12beSStefan Roese * r7: source address, r8: end address, r9: target address 801a47a12beSStefan Roese */ 802a47a12beSStefan Roese .globl trap_init 803a47a12beSStefan Roesetrap_init: 804a47a12beSStefan Roese mflr r4 /* save link register */ 805a47a12beSStefan Roese GET_GOT 806a47a12beSStefan Roese lwz r7, GOT(_start) 807a47a12beSStefan Roese lwz r8, GOT(_end_of_vectors) 808a47a12beSStefan Roese 809a47a12beSStefan Roese li r9, 0x100 /* reset vector always at 0x100 */ 810a47a12beSStefan Roese 811a47a12beSStefan Roese cmplw 0, r7, r8 812a47a12beSStefan Roese bgelr /* return if r7>=r8 - just in case */ 813a47a12beSStefan Roese1: 814a47a12beSStefan Roese lwz r0, 0(r7) 815a47a12beSStefan Roese stw r0, 0(r9) 816a47a12beSStefan Roese addi r7, r7, 4 817a47a12beSStefan Roese addi r9, r9, 4 818a47a12beSStefan Roese cmplw 0, r7, r8 819a47a12beSStefan Roese bne 1b 820a47a12beSStefan Roese 821a47a12beSStefan Roese /* 822a47a12beSStefan Roese * relocate `hdlr' and `int_return' entries 823a47a12beSStefan Roese */ 824a47a12beSStefan Roese li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET 825a47a12beSStefan Roese li r8, Alignment - _start + EXC_OFF_SYS_RESET 826a47a12beSStefan Roese2: 827a47a12beSStefan Roese bl trap_reloc 828a47a12beSStefan Roese addi r7, r7, 0x100 /* next exception vector */ 829a47a12beSStefan Roese cmplw 0, r7, r8 830a47a12beSStefan Roese blt 2b 831a47a12beSStefan Roese 832a47a12beSStefan Roese li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET 833a47a12beSStefan Roese bl trap_reloc 834a47a12beSStefan Roese 835a47a12beSStefan Roese li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET 836a47a12beSStefan Roese bl trap_reloc 837a47a12beSStefan Roese 838a47a12beSStefan Roese li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET 839a47a12beSStefan Roese li r8, SystemCall - _start + EXC_OFF_SYS_RESET 840a47a12beSStefan Roese3: 841a47a12beSStefan Roese bl trap_reloc 842a47a12beSStefan Roese addi r7, r7, 0x100 /* next exception vector */ 843a47a12beSStefan Roese cmplw 0, r7, r8 844a47a12beSStefan Roese blt 3b 845a47a12beSStefan Roese 846a47a12beSStefan Roese li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET 847a47a12beSStefan Roese li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET 848a47a12beSStefan Roese4: 849a47a12beSStefan Roese bl trap_reloc 850a47a12beSStefan Roese addi r7, r7, 0x100 /* next exception vector */ 851a47a12beSStefan Roese cmplw 0, r7, r8 852a47a12beSStefan Roese blt 4b 853a47a12beSStefan Roese 854a47a12beSStefan Roese /* enable execptions from RAM vectors */ 855a47a12beSStefan Roese mfmsr r7 856a47a12beSStefan Roese li r8,MSR_IP 857a47a12beSStefan Roese andc r7,r7,r8 858a47a12beSStefan Roese ori r7,r7,MSR_ME /* Enable Machine Check */ 859a47a12beSStefan Roese mtmsr r7 860a47a12beSStefan Roese 861a47a12beSStefan Roese mtlr r4 /* restore link register */ 862a47a12beSStefan Roese blr 863a47a12beSStefan Roese 864a47a12beSStefan Roese.globl enable_ext_addr 865a47a12beSStefan Roeseenable_ext_addr: 866a47a12beSStefan Roese mfspr r0, HID0 867a47a12beSStefan Roese lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h 868a47a12beSStefan Roese ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l 869a47a12beSStefan Roese mtspr HID0, r0 870a47a12beSStefan Roese sync 871a47a12beSStefan Roese isync 872a47a12beSStefan Roese blr 873a47a12beSStefan Roese 874a47a12beSStefan Roese#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 875a47a12beSStefan Roese.globl setup_ccsrbar 876a47a12beSStefan Roesesetup_ccsrbar: 877a47a12beSStefan Roese /* Special sequence needed to update CCSRBAR itself */ 878a47a12beSStefan Roese lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h 879a47a12beSStefan Roese ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l 880a47a12beSStefan Roese 881a47a12beSStefan Roese lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h 882a47a12beSStefan Roese ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l 883a47a12beSStefan Roese srwi r5,r5,12 884a47a12beSStefan Roese li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l 885a47a12beSStefan Roese rlwimi r5,r6,20,8,11 886a47a12beSStefan Roese stw r5, 0(r4) /* Store physical value of CCSR */ 887a47a12beSStefan Roese isync 888a47a12beSStefan Roese 88914d0a02aSWolfgang Denk lis r5, CONFIG_SYS_TEXT_BASE@h 89014d0a02aSWolfgang Denk ori r5,r5,CONFIG_SYS_TEXT_BASE@l 891a47a12beSStefan Roese lwz r5, 0(r5) 892a47a12beSStefan Roese isync 893a47a12beSStefan Roese 894a47a12beSStefan Roese /* Use VA of CCSR to do read */ 895a47a12beSStefan Roese lis r3, CONFIG_SYS_CCSRBAR@h 896a47a12beSStefan Roese lwz r5, CONFIG_SYS_CCSRBAR@l(r3) 897a47a12beSStefan Roese isync 898a47a12beSStefan Roese 899a47a12beSStefan Roese blr 900a47a12beSStefan Roese#endif 901a47a12beSStefan Roese 902a47a12beSStefan Roese#ifdef CONFIG_SYS_INIT_RAM_LOCK 903a47a12beSStefan Roeselock_ram_in_cache: 904a47a12beSStefan Roese /* Allocate Initial RAM in data cache. 905a47a12beSStefan Roese */ 906a47a12beSStefan Roese lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 907a47a12beSStefan Roese ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 908553f0982SWolfgang Denk li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 909a47a12beSStefan Roese (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 910a47a12beSStefan Roese mtctr r4 911a47a12beSStefan Roese1: 912a47a12beSStefan Roese dcbz r0, r3 913a47a12beSStefan Roese addi r3, r3, 32 914a47a12beSStefan Roese bdnz 1b 915a47a12beSStefan Roese#if 1 916a47a12beSStefan Roese/* Lock the data cache */ 917a47a12beSStefan Roese mfspr r0, HID0 918a47a12beSStefan Roese ori r0, r0, 0x1000 919a47a12beSStefan Roese sync 920a47a12beSStefan Roese mtspr HID0, r0 921a47a12beSStefan Roese sync 922a47a12beSStefan Roese blr 923a47a12beSStefan Roese#endif 924a47a12beSStefan Roese#if 0 925a47a12beSStefan Roese /* Lock the first way of the data cache */ 926a47a12beSStefan Roese mfspr r0, LDSTCR 927a47a12beSStefan Roese ori r0, r0, 0x0080 928a47a12beSStefan Roese#if defined(CONFIG_ALTIVEC) 929a47a12beSStefan Roese dssall 930a47a12beSStefan Roese#endif 931a47a12beSStefan Roese sync 932a47a12beSStefan Roese mtspr LDSTCR, r0 933a47a12beSStefan Roese sync 934a47a12beSStefan Roese isync 935a47a12beSStefan Roese blr 936a47a12beSStefan Roese#endif 937a47a12beSStefan Roese 938a47a12beSStefan Roese.globl unlock_ram_in_cache 939a47a12beSStefan Roeseunlock_ram_in_cache: 940a47a12beSStefan Roese /* invalidate the INIT_RAM section */ 941a47a12beSStefan Roese lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h 942a47a12beSStefan Roese ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l 943553f0982SWolfgang Denk li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ 944a47a12beSStefan Roese (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 945a47a12beSStefan Roese mtctr r4 946a47a12beSStefan Roese1: icbi r0, r3 947a47a12beSStefan Roese addi r3, r3, 32 948a47a12beSStefan Roese bdnz 1b 949a47a12beSStefan Roese sync /* Wait for all icbi to complete on bus */ 950a47a12beSStefan Roese isync 951a47a12beSStefan Roese#if 1 952a47a12beSStefan Roese/* Unlock the data cache and invalidate it */ 953a47a12beSStefan Roese mfspr r0, HID0 954a47a12beSStefan Roese li r3,0x1000 955a47a12beSStefan Roese andc r0,r0,r3 956a47a12beSStefan Roese li r3,0x0400 957a47a12beSStefan Roese or r0,r0,r3 958a47a12beSStefan Roese sync 959a47a12beSStefan Roese mtspr HID0, r0 960a47a12beSStefan Roese sync 961a47a12beSStefan Roese blr 962a47a12beSStefan Roese#endif 963a47a12beSStefan Roese#if 0 964a47a12beSStefan Roese /* Unlock the first way of the data cache */ 965a47a12beSStefan Roese mfspr r0, LDSTCR 966a47a12beSStefan Roese li r3,0x0080 967a47a12beSStefan Roese andc r0,r0,r3 968a47a12beSStefan Roese#ifdef CONFIG_ALTIVEC 969a47a12beSStefan Roese dssall 970a47a12beSStefan Roese#endif 971a47a12beSStefan Roese sync 972a47a12beSStefan Roese mtspr LDSTCR, r0 973a47a12beSStefan Roese sync 974a47a12beSStefan Roese isync 975a47a12beSStefan Roese li r3,0x0400 976a47a12beSStefan Roese or r0,r0,r3 977a47a12beSStefan Roese sync 978a47a12beSStefan Roese mtspr HID0, r0 979a47a12beSStefan Roese sync 980a47a12beSStefan Roese blr 981a47a12beSStefan Roese#endif 982a47a12beSStefan Roese#endif 983