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Searched refs:mmio_base (Results 1 – 25 of 172) sorted by relevance

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/openbmc/linux/drivers/input/keyboard/
H A Dimx_keypad.c49 void __iomem *mmio_base; member
94 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
96 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
98 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
100 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
104 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
106 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
113 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
115 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
127 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
[all …]
/openbmc/linux/drivers/pwm/
H A Dpwm-tiecap.c37 void __iomem *mmio_base; member
75 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_config()
80 writew(value, pc->mmio_base + ECCTL2); in ecap_pwm_config()
84 writel(duty_cycles, pc->mmio_base + CAP2); in ecap_pwm_config()
85 writel(period_cycles, pc->mmio_base + CAP1); in ecap_pwm_config()
92 writel(duty_cycles, pc->mmio_base + CAP4); in ecap_pwm_config()
93 writel(period_cycles, pc->mmio_base + CAP3); in ecap_pwm_config()
97 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_config()
100 writew(value, pc->mmio_base + ECCTL2); in ecap_pwm_config()
116 value = readw(pc->mmio_base + ECCTL2); in ecap_pwm_set_polarity()
[all …]
H A Dpwm-tiehrpwm.c110 void __iomem *mmio_base; member
211 ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val); in configure_polarity()
278 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval); in ehrpwm_pwm_config()
285 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW); in ehrpwm_pwm_config()
287 ehrpwm_write(pc->mmio_base, TBPRD, period_cycles); in ehrpwm_pwm_config()
290 ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK, in ehrpwm_pwm_config()
300 ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles); in ehrpwm_pwm_config()
338 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, in ehrpwm_pwm_enable()
341 ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val); in ehrpwm_pwm_enable()
372 ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK, in ehrpwm_pwm_disable()
[all …]
H A Dpwm-imx27.c86 void __iomem *mmio_base; member
134 val = readl(imx->mmio_base + MX3_PWMCR); in pwm_imx27_get_state()
154 val = readl(imx->mmio_base + MX3_PWMPR); in pwm_imx27_get_state()
166 val = readl(imx->mmio_base + MX3_PWMSAR); in pwm_imx27_get_state()
185 writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR); in pwm_imx27_sw_reset()
188 cr = readl(imx->mmio_base + MX3_PWMCR); in pwm_imx27_sw_reset()
205 sr = readl(imx->mmio_base + MX3_PWMSR); in pwm_imx27_wait_fifo_slot()
212 sr = readl(imx->mmio_base + MX3_PWMSR); in pwm_imx27_wait_fifo_slot()
270 val = readl(imx->mmio_base + MX3_PWMPR); in pwm_imx27_apply()
272 cr = readl(imx->mmio_base + MX3_PWMCR); in pwm_imx27_apply()
[all …]
H A Dpwm-imx1.c30 void __iomem *mmio_base; member
85 max = readl(imx->mmio_base + MX1_PWMP); in pwm_imx1_config()
88 writel(max - p, imx->mmio_base + MX1_PWMS); in pwm_imx1_config()
103 value = readl(imx->mmio_base + MX1_PWMC); in pwm_imx1_enable()
105 writel(value, imx->mmio_base + MX1_PWMC); in pwm_imx1_enable()
115 value = readl(imx->mmio_base + MX1_PWMC); in pwm_imx1_disable()
117 writel(value, imx->mmio_base + MX1_PWMC); in pwm_imx1_disable()
180 imx->mmio_base = devm_platform_ioremap_resource(pdev, 0); in pwm_imx1_probe()
181 if (IS_ERR(imx->mmio_base)) in pwm_imx1_probe()
182 return PTR_ERR(imx->mmio_base); in pwm_imx1_probe()
H A Dpwm-pxa.c56 void __iomem *mmio_base; member
96 writel(prescale | PWMCR_SD, pc->mmio_base + offset + PWMCR); in pxa_pwm_config()
97 writel(dc, pc->mmio_base + offset + PWMDCR); in pxa_pwm_config()
98 writel(pv, pc->mmio_base + offset + PWMPCR); in pxa_pwm_config()
189 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in pwm_probe()
190 if (IS_ERR(pc->mmio_base)) in pwm_probe()
191 return PTR_ERR(pc->mmio_base); in pwm_probe()
H A Dpwm-spear.c54 void __iomem *mmio_base; member
67 return readl_relaxed(chip->mmio_base + (num << 4) + offset); in spear_pwm_readl()
74 writel_relaxed(val, chip->mmio_base + (num << 4) + offset); in spear_pwm_writel()
206 pc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in spear_pwm_probe()
207 if (IS_ERR(pc->mmio_base)) in spear_pwm_probe()
208 return PTR_ERR(pc->mmio_base); in spear_pwm_probe()
234 val = readl_relaxed(pc->mmio_base + PWMMCR); in spear_pwm_probe()
236 writel_relaxed(val, pc->mmio_base + PWMMCR); in spear_pwm_probe()
/openbmc/linux/drivers/edac/
H A Dal_mc_edac.c57 void __iomem *mmio_base; member
83 eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT); in handle_ce()
88 ecccaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR0); in handle_ce()
89 ecccaddr1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_ADDR1); in handle_ce()
90 ecccsyn0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND0); in handle_ce()
91 ecccsyn1 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND1); in handle_ce()
92 ecccsyn2 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_CE_SYND2); in handle_ce()
95 al_mc->mmio_base + AL_MC_ECC_CLEAR); in handle_ce()
128 eccerrcnt = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_ERR_COUNT); in handle_ue()
133 eccuaddr0 = readl_relaxed(al_mc->mmio_base + AL_MC_ECC_UE_ADDR0); in handle_ue()
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dpio.h72 u16 mmio_base; member
101 u16 mmio_base; member
111 return b43_read16(q->dev, q->mmio_base + offset); in b43_piotx_read16()
116 return b43_read32(q->dev, q->mmio_base + offset); in b43_piotx_read32()
122 b43_write16(q->dev, q->mmio_base + offset, value); in b43_piotx_write16()
128 b43_write32(q->dev, q->mmio_base + offset, value); in b43_piotx_write32()
134 return b43_read16(q->dev, q->mmio_base + offset); in b43_piorx_read16()
139 return b43_read32(q->dev, q->mmio_base + offset); in b43_piorx_read32()
145 b43_write16(q->dev, q->mmio_base + offset, value); in b43_piorx_write16()
151 b43_write32(q->dev, q->mmio_base + offset, value); in b43_piorx_write32()
/openbmc/linux/drivers/ata/
H A Dsata_sil.c254 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; in sil_bmdma_stop() local
255 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; in sil_bmdma_stop()
280 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; in sil_bmdma_start() local
281 void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; in sil_bmdma_start()
348 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; in sil_set_mode() local
349 void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode; in sil_set_mode()
509 void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; in sil_interrupt() local
517 u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); in sil_interrupt()
538 void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; in sil_freeze() local
542 writel(0, mmio_base + sil_port[ap->port_no].sien); in sil_freeze()
[all …]
H A Dpata_pdc2027x.c461 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; in pdc_read_counter() local
467 bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; in pdc_read_counter()
468 bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; in pdc_read_counter()
471 bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff; in pdc_read_counter()
472 bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff; in pdc_read_counter()
502 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR]; in pdc_adjust_pll() local
521 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); in pdc_adjust_pll()
560 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL); in pdc_adjust_pll()
561 ioread16(mmio_base + PDC_PLL_CTL); /* flush */ in pdc_adjust_pll()
570 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL); in pdc_adjust_pll()
[all …]
H A Dsata_qstor.c192 u8 __iomem *mmio_base = qs_mmio_base(ap->host); in qs_freeze() local
194 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */ in qs_freeze()
200 u8 __iomem *mmio_base = qs_mmio_base(ap->host); in qs_thaw() local
203 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */ in qs_thaw()
354 u8 __iomem *mmio_base = qs_mmio_base(host); in qs_intr_pkt() local
357 u32 sff0 = readl(mmio_base + QS_HST_SFF); in qs_intr_pkt()
358 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4); in qs_intr_pkt()
460 void __iomem *mmio_base = qs_mmio_base(ap->host); in qs_port_start() local
461 void __iomem *chan = mmio_base + (ap->port_no * 0x4000); in qs_port_start()
482 void __iomem *mmio_base = qs_mmio_base(host); in qs_host_stop() local
[all …]
H A Dpata_sil680.c340 void __iomem *mmio_base; in sil680_init_one() local
380 mmio_base = host->iomap[SIL680_MMIO_BAR]; in sil680_init_one()
381 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00; in sil680_init_one()
382 host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80; in sil680_init_one()
383 host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a; in sil680_init_one()
384 host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a; in sil680_init_one()
386 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08; in sil680_init_one()
387 host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0; in sil680_init_one()
388 host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca; in sil680_init_one()
389 host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca; in sil680_init_one()
H A Dsata_inic162x.c234 void __iomem *mmio_base; member
268 return hpriv->mmio_base + ap->port_no * PORT_SIZE; in inic_port_base()
426 host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT); in inic_interrupt()
752 static int init_controller(void __iomem *mmio_base, u16 hctl) in init_controller() argument
762 writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL); in init_controller()
763 readw(mmio_base + HOST_CTL); /* flush */ in init_controller()
767 val = readw(mmio_base + HOST_CTL); in init_controller()
777 void __iomem *port_base = mmio_base + i * PORT_SIZE; in init_controller()
784 writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL); in init_controller()
785 val = readw(mmio_base + HOST_IRQ_MASK); in init_controller()
[all …]
/openbmc/linux/drivers/usb/host/
H A Dohci-pxa27x.c121 void __iomem *mmio_base; member
140 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); in pxa27x_ohci_select_pmm()
141 uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB); in pxa27x_ohci_select_pmm()
165 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); in pxa27x_ohci_select_pmm()
166 __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB); in pxa27x_ohci_select_pmm()
221 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); in pxa27x_setup_hc()
222 uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA); in pxa27x_setup_hc()
254 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); in pxa27x_setup_hc()
255 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); in pxa27x_setup_hc()
260 uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR); in pxa27x_reset_hc()
[all …]
/openbmc/linux/drivers/clk/mmp/
H A Dclk-audio.c61 void __iomem *mmio_base; member
125 aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0); in audio_pll_recalc_rate()
133 aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1); in audio_pll_recalc_rate()
216 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL0); in audio_pll_set_rate()
220 writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL1); in audio_pll_set_rate()
257 priv->sspa_mux.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
267 priv->sysclk_div.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
280 priv->sysclk_gate.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
288 priv->sspa0_div.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
301 priv->sspa0_gate.reg = priv->mmio_base + SSPA_AUD_CTRL; in register_clocks()
[all …]
/openbmc/linux/drivers/thermal/
H A Dthermal_mmio.c12 void __iomem *mmio_base; member
13 u32 (*read_mmio)(void __iomem *mmio_base);
18 static u32 thermal_mmio_readb(void __iomem *mmio_base) in thermal_mmio_readb() argument
20 return readb(mmio_base); in thermal_mmio_readb()
28 t = sensor->read_mmio(sensor->mmio_base) & sensor->mask; in thermal_mmio_get_temperature()
53 sensor->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); in thermal_mmio_probe()
54 if (IS_ERR(sensor->mmio_base)) in thermal_mmio_probe()
55 return PTR_ERR(sensor->mmio_base); in thermal_mmio_probe()
/openbmc/linux/drivers/misc/vmw_vmci/
H A Dvmci_guest.c55 void __iomem *mmio_base; member
104 if (dev->mmio_base != NULL) in vmci_read_reg()
105 return readl(dev->mmio_base + reg); in vmci_read_reg()
111 if (dev->mmio_base != NULL) in vmci_write_reg()
112 writel(val, dev->mmio_base + reg); in vmci_write_reg()
120 if (vmci_dev->mmio_base == NULL) in vmci_read_data()
152 if (dev->mmio_base != NULL) { in vmci_write_data()
312 bool is_io_port = vmci_dev->mmio_base == NULL; in vmci_dispatch_dgs()
555 if (vmci_dev->mmio_base != NULL) { in vmci_free_dg_buffers()
579 void __iomem *mmio_base = NULL; in vmci_guest_probe_device() local
[all …]
/openbmc/linux/drivers/rtc/
H A Drtc-ep93xx.c29 void __iomem *mmio_base; member
39 comp = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_SWCOMP); in ep93xx_rtc_get_swcomp()
57 time = readl(ep93xx_rtc->mmio_base + EP93XX_RTC_DATA); in ep93xx_rtc_read_time()
68 writel(secs + 1, ep93xx_rtc->mmio_base + EP93XX_RTC_LOAD); in ep93xx_rtc_set_time()
131 ep93xx_rtc->mmio_base = devm_platform_ioremap_resource(pdev, 0); in ep93xx_rtc_probe()
132 if (IS_ERR(ep93xx_rtc->mmio_base)) in ep93xx_rtc_probe()
133 return PTR_ERR(ep93xx_rtc->mmio_base); in ep93xx_rtc_probe()
/openbmc/qemu/hw/core/
H A Dsysbus-fdt.c222 uint64_t mmio_base, irq_number; in add_calxeda_midway_xgmac_fdt_node() local
226 mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); in add_calxeda_midway_xgmac_fdt_node()
228 vbasedev->name, mmio_base); in add_calxeda_midway_xgmac_fdt_node()
239 mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, i); in add_calxeda_midway_xgmac_fdt_node()
240 reg_attr[2 * i] = cpu_to_be32(mmio_base); in add_calxeda_midway_xgmac_fdt_node()
304 uint64_t mmio_base, irq_number; in add_amd_xgbe_fdt_node() local
361 mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); in add_amd_xgbe_fdt_node()
363 vbasedev->name, mmio_base); in add_amd_xgbe_fdt_node()
377 mmio_base = platform_bus_get_mmio_addr(pbus, sbdev, i); in add_amd_xgbe_fdt_node()
378 reg_attr[2 * i] = cpu_to_be32(mmio_base); in add_amd_xgbe_fdt_node()
[all …]
/openbmc/linux/drivers/video/fbdev/mb862xx/
H A Dmb862xxfbdrv.c633 par->host = par->mmio_base; in mb862xx_gdc_init()
634 par->i2c = par->mmio_base + MB862XX_I2C_BASE; in mb862xx_gdc_init()
635 par->disp = par->mmio_base + MB862XX_DISP_BASE; in mb862xx_gdc_init()
636 par->cap = par->mmio_base + MB862XX_CAP_BASE; in mb862xx_gdc_init()
637 par->draw = par->mmio_base + MB862XX_DRAW_BASE; in mb862xx_gdc_init()
638 par->geo = par->mmio_base + MB862XX_GEO_BASE; in mb862xx_gdc_init()
639 par->pio = par->mmio_base + MB862XX_PIO_BASE; in mb862xx_gdc_init()
725 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len); in of_platform_mb862xx_probe()
726 if (par->mmio_base == NULL) { in of_platform_mb862xx_probe()
772 iounmap(par->mmio_base); in of_platform_mb862xx_probe()
[all …]
/openbmc/linux/drivers/soundwire/
H A Dintel_init.c65 link->mmio_base = res->mmio_base; in intel_link_dev_register()
67 link->registers = res->mmio_base + SDW_LINK_BASE in intel_link_dev_register()
70 link->shim = res->mmio_base + res->shim_base; in intel_link_dev_register()
71 link->alh = res->mmio_base + res->alh_base; in intel_link_dev_register()
74 link->registers = res->mmio_base + SDW_IP_BASE(link_id); in intel_link_dev_register()
76 link->shim = res->mmio_base + SDW_SHIM2_GENERIC_BASE(link_id); in intel_link_dev_register()
77 link->shim_vs = res->mmio_base + SDW_SHIM2_VS_BASE(link_id); in intel_link_dev_register()
205 ctx->mmio_base = res->mmio_base; in sdw_intel_probe_controller()
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dbgmac.c46 if (!ring->mmio_base) in bgmac_dma_tx_reset()
53 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, in bgmac_dma_tx_reset()
56 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); in bgmac_dma_tx_reset()
68 ring->mmio_base, val); in bgmac_dma_tx_reset()
71 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0); in bgmac_dma_tx_reset()
73 ring->mmio_base + BGMAC_DMA_TX_STATUS, in bgmac_dma_tx_reset()
77 ring->mmio_base); in bgmac_dma_tx_reset()
79 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS); in bgmac_dma_tx_reset()
82 ring->mmio_base); in bgmac_dma_tx_reset()
91 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); in bgmac_dma_tx_enable()
[all …]
/openbmc/linux/drivers/thermal/intel/int340x_thermal/
H A Dprocessor_thermal_mbox.c35 data = readl(proc_priv->mmio_base + MBOX_OFFSET_INTERFACE); in wait_for_mbox_ready()
61 writel(data, (proc_priv->mmio_base + MBOX_OFFSET_DATA)); in send_mbox_write_cmd()
64 writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE)); in send_mbox_write_cmd()
89 writel(reg_data, (proc_priv->mmio_base + MBOX_OFFSET_INTERFACE)); in send_mbox_read_cmd()
96 *resp = readl(proc_priv->mmio_base + MBOX_OFFSET_DATA); in send_mbox_read_cmd()
98 *resp = readq(proc_priv->mmio_base + MBOX_OFFSET_DATA); in send_mbox_read_cmd()
/openbmc/u-boot/drivers/video/
H A Dati_radeon_fb.h55 void *mmio_base; member
66 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
67 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
68 #define INREG16(addr) readw((rinfo->mmio_base)+addr)
69 #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
70 #define INREG(addr) readl((rinfo->mmio_base)+addr)
71 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)

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