1725262d2SLubomir Rintel // SPDX-License-Identifier: GPL-2.0-or-later
2725262d2SLubomir Rintel /*
3725262d2SLubomir Rintel * MMP Audio Clock Controller driver
4725262d2SLubomir Rintel *
5725262d2SLubomir Rintel * Copyright (C) 2020 Lubomir Rintel <lkundrak@v3.sk>
6725262d2SLubomir Rintel */
7725262d2SLubomir Rintel
8725262d2SLubomir Rintel #include <linux/clk-provider.h>
9725262d2SLubomir Rintel #include <linux/io.h>
10725262d2SLubomir Rintel #include <linux/module.h>
11725262d2SLubomir Rintel #include <linux/platform_device.h>
12725262d2SLubomir Rintel #include <linux/pm_clock.h>
13725262d2SLubomir Rintel #include <linux/pm_runtime.h>
14725262d2SLubomir Rintel #include <linux/slab.h>
15725262d2SLubomir Rintel #include <dt-bindings/clock/marvell,mmp2-audio.h>
16725262d2SLubomir Rintel
17725262d2SLubomir Rintel /* Audio Controller Registers */
18725262d2SLubomir Rintel #define SSPA_AUD_CTRL 0x04
19725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0 0x08
20725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL1 0x0c
21725262d2SLubomir Rintel
22725262d2SLubomir Rintel /* SSPA Audio Control Register */
23725262d2SLubomir Rintel #define SSPA_AUD_CTRL_SYSCLK_SHIFT 0
24725262d2SLubomir Rintel #define SSPA_AUD_CTRL_SYSCLK_DIV_SHIFT 1
25725262d2SLubomir Rintel #define SSPA_AUD_CTRL_SSPA0_MUX_SHIFT 7
26725262d2SLubomir Rintel #define SSPA_AUD_CTRL_SSPA0_SHIFT 8
27725262d2SLubomir Rintel #define SSPA_AUD_CTRL_SSPA0_DIV_SHIFT 9
28725262d2SLubomir Rintel #define SSPA_AUD_CTRL_SSPA1_SHIFT 16
29725262d2SLubomir Rintel #define SSPA_AUD_CTRL_SSPA1_DIV_SHIFT 17
30725262d2SLubomir Rintel #define SSPA_AUD_CTRL_SSPA1_MUX_SHIFT 23
31725262d2SLubomir Rintel #define SSPA_AUD_CTRL_DIV_MASK 0x7e
32725262d2SLubomir Rintel
33725262d2SLubomir Rintel /* SSPA Audio PLL Control 0 Register */
34725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO_MASK (0x7 << 28)
35725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(x) ((x) << 28)
36725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0_FRACT_MASK (0xfffff << 8)
37725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0_FRACT(x) ((x) << 8)
38725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0_ENA_DITHER (1 << 7)
39725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0_ICP_2UA (0 << 5)
40725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0_ICP_5UA (1 << 5)
41725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0_ICP_7UA (2 << 5)
42725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0_ICP_10UA (3 << 5)
43725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0_DIV_FBCCLK_MASK (0x3 << 3)
44725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(x) ((x) << 3)
45725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0_DIV_MCLK_MASK (0x1 << 2)
46725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0_DIV_MCLK(x) ((x) << 2)
47725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0_PD_OVPROT_DIS (1 << 1)
48725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL0_PU (1 << 0)
49725262d2SLubomir Rintel
50725262d2SLubomir Rintel /* SSPA Audio PLL Control 1 Register */
51725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL1_SEL_FAST_CLK (1 << 24)
52725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL1_CLK_SEL_MASK (1 << 11)
53725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL1_CLK_SEL_AUDIO_PLL (1 << 11)
54725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL1_CLK_SEL_VCXO (0 << 11)
55725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN_MASK (0x7ff << 0)
56725262d2SLubomir Rintel #define SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(x) ((x) << 0)
57725262d2SLubomir Rintel
58*46c13513SDuje Mihanović #define CLK_AUDIO_NR_CLKS 3
59*46c13513SDuje Mihanović
60725262d2SLubomir Rintel struct mmp2_audio_clk {
61725262d2SLubomir Rintel void __iomem *mmio_base;
62725262d2SLubomir Rintel
63725262d2SLubomir Rintel struct clk_hw audio_pll_hw;
64725262d2SLubomir Rintel struct clk_mux sspa_mux;
65725262d2SLubomir Rintel struct clk_mux sspa1_mux;
66725262d2SLubomir Rintel struct clk_divider sysclk_div;
67725262d2SLubomir Rintel struct clk_divider sspa0_div;
68725262d2SLubomir Rintel struct clk_divider sspa1_div;
69725262d2SLubomir Rintel struct clk_gate sysclk_gate;
70725262d2SLubomir Rintel struct clk_gate sspa0_gate;
71725262d2SLubomir Rintel struct clk_gate sspa1_gate;
72725262d2SLubomir Rintel
73725262d2SLubomir Rintel u32 aud_ctrl;
74725262d2SLubomir Rintel u32 aud_pll_ctrl0;
75725262d2SLubomir Rintel u32 aud_pll_ctrl1;
76725262d2SLubomir Rintel
77725262d2SLubomir Rintel spinlock_t lock;
78725262d2SLubomir Rintel
79725262d2SLubomir Rintel /* Must be last */
80725262d2SLubomir Rintel struct clk_hw_onecell_data clk_data;
81725262d2SLubomir Rintel };
82725262d2SLubomir Rintel
83725262d2SLubomir Rintel static const struct {
84725262d2SLubomir Rintel unsigned long parent_rate;
85725262d2SLubomir Rintel unsigned long freq_vco;
86725262d2SLubomir Rintel unsigned char mclk;
87725262d2SLubomir Rintel unsigned char fbcclk;
88725262d2SLubomir Rintel unsigned short fract;
89725262d2SLubomir Rintel } predivs[] = {
90725262d2SLubomir Rintel { 26000000, 135475200, 0, 0, 0x8a18 },
91725262d2SLubomir Rintel { 26000000, 147456000, 0, 1, 0x0da1 },
92725262d2SLubomir Rintel { 38400000, 135475200, 1, 2, 0x8208 },
93725262d2SLubomir Rintel { 38400000, 147456000, 1, 3, 0xaaaa },
94725262d2SLubomir Rintel };
95725262d2SLubomir Rintel
96725262d2SLubomir Rintel static const struct {
97725262d2SLubomir Rintel unsigned char divisor;
98725262d2SLubomir Rintel unsigned char modulo;
99725262d2SLubomir Rintel unsigned char pattern;
100725262d2SLubomir Rintel } postdivs[] = {
101725262d2SLubomir Rintel { 1, 3, 0, },
102725262d2SLubomir Rintel { 2, 5, 0, },
103725262d2SLubomir Rintel { 4, 0, 0, },
104725262d2SLubomir Rintel { 6, 1, 1, },
105725262d2SLubomir Rintel { 8, 1, 0, },
106725262d2SLubomir Rintel { 9, 1, 2, },
107725262d2SLubomir Rintel { 12, 2, 1, },
108725262d2SLubomir Rintel { 16, 2, 0, },
109725262d2SLubomir Rintel { 18, 2, 2, },
110725262d2SLubomir Rintel { 24, 4, 1, },
111725262d2SLubomir Rintel { 36, 4, 2, },
112725262d2SLubomir Rintel { 48, 6, 1, },
113725262d2SLubomir Rintel { 72, 6, 2, },
114725262d2SLubomir Rintel };
115725262d2SLubomir Rintel
audio_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)116725262d2SLubomir Rintel static unsigned long audio_pll_recalc_rate(struct clk_hw *hw,
117725262d2SLubomir Rintel unsigned long parent_rate)
118725262d2SLubomir Rintel {
119725262d2SLubomir Rintel struct mmp2_audio_clk *priv = container_of(hw, struct mmp2_audio_clk, audio_pll_hw);
120725262d2SLubomir Rintel unsigned int prediv;
121725262d2SLubomir Rintel unsigned int postdiv;
122725262d2SLubomir Rintel u32 aud_pll_ctrl0;
123725262d2SLubomir Rintel u32 aud_pll_ctrl1;
124725262d2SLubomir Rintel
125725262d2SLubomir Rintel aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0);
126725262d2SLubomir Rintel aud_pll_ctrl0 &= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO_MASK |
127725262d2SLubomir Rintel SSPA_AUD_PLL_CTRL0_FRACT_MASK |
128725262d2SLubomir Rintel SSPA_AUD_PLL_CTRL0_ENA_DITHER |
129725262d2SLubomir Rintel SSPA_AUD_PLL_CTRL0_DIV_FBCCLK_MASK |
130725262d2SLubomir Rintel SSPA_AUD_PLL_CTRL0_DIV_MCLK_MASK |
131725262d2SLubomir Rintel SSPA_AUD_PLL_CTRL0_PU;
132725262d2SLubomir Rintel
133725262d2SLubomir Rintel aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1);
134725262d2SLubomir Rintel aud_pll_ctrl1 &= SSPA_AUD_PLL_CTRL1_CLK_SEL_MASK |
135725262d2SLubomir Rintel SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN_MASK;
136725262d2SLubomir Rintel
137725262d2SLubomir Rintel for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) {
138725262d2SLubomir Rintel if (predivs[prediv].parent_rate != parent_rate)
139725262d2SLubomir Rintel continue;
140725262d2SLubomir Rintel for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) {
141725262d2SLubomir Rintel unsigned long freq;
142725262d2SLubomir Rintel u32 val;
143725262d2SLubomir Rintel
144725262d2SLubomir Rintel val = SSPA_AUD_PLL_CTRL0_ENA_DITHER;
145725262d2SLubomir Rintel val |= SSPA_AUD_PLL_CTRL0_PU;
146725262d2SLubomir Rintel val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo);
147725262d2SLubomir Rintel val |= SSPA_AUD_PLL_CTRL0_FRACT(predivs[prediv].fract);
148725262d2SLubomir Rintel val |= SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(predivs[prediv].fbcclk);
149725262d2SLubomir Rintel val |= SSPA_AUD_PLL_CTRL0_DIV_MCLK(predivs[prediv].mclk);
150725262d2SLubomir Rintel if (val != aud_pll_ctrl0)
151725262d2SLubomir Rintel continue;
152725262d2SLubomir Rintel
153725262d2SLubomir Rintel val = SSPA_AUD_PLL_CTRL1_CLK_SEL_AUDIO_PLL;
154725262d2SLubomir Rintel val |= SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(postdivs[postdiv].pattern);
155725262d2SLubomir Rintel if (val != aud_pll_ctrl1)
156725262d2SLubomir Rintel continue;
157725262d2SLubomir Rintel
158725262d2SLubomir Rintel freq = predivs[prediv].freq_vco;
159725262d2SLubomir Rintel freq /= postdivs[postdiv].divisor;
160725262d2SLubomir Rintel return freq;
161725262d2SLubomir Rintel }
162725262d2SLubomir Rintel }
163725262d2SLubomir Rintel
164725262d2SLubomir Rintel return 0;
165725262d2SLubomir Rintel }
166725262d2SLubomir Rintel
audio_pll_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)167725262d2SLubomir Rintel static long audio_pll_round_rate(struct clk_hw *hw, unsigned long rate,
168725262d2SLubomir Rintel unsigned long *parent_rate)
169725262d2SLubomir Rintel {
170725262d2SLubomir Rintel unsigned int prediv;
171725262d2SLubomir Rintel unsigned int postdiv;
172725262d2SLubomir Rintel long rounded = 0;
173725262d2SLubomir Rintel
174725262d2SLubomir Rintel for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) {
175725262d2SLubomir Rintel if (predivs[prediv].parent_rate != *parent_rate)
176725262d2SLubomir Rintel continue;
177725262d2SLubomir Rintel for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) {
178725262d2SLubomir Rintel long freq = predivs[prediv].freq_vco;
179725262d2SLubomir Rintel
180725262d2SLubomir Rintel freq /= postdivs[postdiv].divisor;
181725262d2SLubomir Rintel if (freq == rate)
182725262d2SLubomir Rintel return rate;
183725262d2SLubomir Rintel if (freq < rate)
184725262d2SLubomir Rintel continue;
185725262d2SLubomir Rintel if (rounded && freq > rounded)
186725262d2SLubomir Rintel continue;
187725262d2SLubomir Rintel rounded = freq;
188725262d2SLubomir Rintel }
189725262d2SLubomir Rintel }
190725262d2SLubomir Rintel
191725262d2SLubomir Rintel return rounded;
192725262d2SLubomir Rintel }
193725262d2SLubomir Rintel
audio_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)194725262d2SLubomir Rintel static int audio_pll_set_rate(struct clk_hw *hw, unsigned long rate,
195725262d2SLubomir Rintel unsigned long parent_rate)
196725262d2SLubomir Rintel {
197725262d2SLubomir Rintel struct mmp2_audio_clk *priv = container_of(hw, struct mmp2_audio_clk, audio_pll_hw);
198725262d2SLubomir Rintel unsigned int prediv;
199725262d2SLubomir Rintel unsigned int postdiv;
200725262d2SLubomir Rintel unsigned long val;
201725262d2SLubomir Rintel
202725262d2SLubomir Rintel for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) {
203725262d2SLubomir Rintel if (predivs[prediv].parent_rate != parent_rate)
204725262d2SLubomir Rintel continue;
205725262d2SLubomir Rintel
206725262d2SLubomir Rintel for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) {
207725262d2SLubomir Rintel if (rate * postdivs[postdiv].divisor != predivs[prediv].freq_vco)
208725262d2SLubomir Rintel continue;
209725262d2SLubomir Rintel
210725262d2SLubomir Rintel val = SSPA_AUD_PLL_CTRL0_ENA_DITHER;
211725262d2SLubomir Rintel val |= SSPA_AUD_PLL_CTRL0_PU;
212725262d2SLubomir Rintel val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo);
213725262d2SLubomir Rintel val |= SSPA_AUD_PLL_CTRL0_FRACT(predivs[prediv].fract);
214725262d2SLubomir Rintel val |= SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(predivs[prediv].fbcclk);
215725262d2SLubomir Rintel val |= SSPA_AUD_PLL_CTRL0_DIV_MCLK(predivs[prediv].mclk);
216725262d2SLubomir Rintel writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL0);
217725262d2SLubomir Rintel
218725262d2SLubomir Rintel val = SSPA_AUD_PLL_CTRL1_CLK_SEL_AUDIO_PLL;
219725262d2SLubomir Rintel val |= SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(postdivs[postdiv].pattern);
220725262d2SLubomir Rintel writel(val, priv->mmio_base + SSPA_AUD_PLL_CTRL1);
221725262d2SLubomir Rintel
222725262d2SLubomir Rintel return 0;
223725262d2SLubomir Rintel }
224725262d2SLubomir Rintel }
225725262d2SLubomir Rintel
226725262d2SLubomir Rintel return -ERANGE;
227725262d2SLubomir Rintel }
228725262d2SLubomir Rintel
229725262d2SLubomir Rintel static const struct clk_ops audio_pll_ops = {
230725262d2SLubomir Rintel .recalc_rate = audio_pll_recalc_rate,
231725262d2SLubomir Rintel .round_rate = audio_pll_round_rate,
232725262d2SLubomir Rintel .set_rate = audio_pll_set_rate,
233725262d2SLubomir Rintel };
234725262d2SLubomir Rintel
register_clocks(struct mmp2_audio_clk * priv,struct device * dev)235725262d2SLubomir Rintel static int register_clocks(struct mmp2_audio_clk *priv, struct device *dev)
236725262d2SLubomir Rintel {
237725262d2SLubomir Rintel const struct clk_parent_data sspa_mux_parents[] = {
238725262d2SLubomir Rintel { .hw = &priv->audio_pll_hw },
239725262d2SLubomir Rintel { .fw_name = "i2s0" },
240725262d2SLubomir Rintel };
241725262d2SLubomir Rintel const struct clk_parent_data sspa1_mux_parents[] = {
242725262d2SLubomir Rintel { .hw = &priv->audio_pll_hw },
243725262d2SLubomir Rintel { .fw_name = "i2s1" },
244725262d2SLubomir Rintel };
245725262d2SLubomir Rintel int ret;
246725262d2SLubomir Rintel
247725262d2SLubomir Rintel priv->audio_pll_hw.init = CLK_HW_INIT_FW_NAME("audio_pll",
248725262d2SLubomir Rintel "vctcxo", &audio_pll_ops,
249725262d2SLubomir Rintel CLK_SET_RATE_PARENT);
250725262d2SLubomir Rintel ret = devm_clk_hw_register(dev, &priv->audio_pll_hw);
251725262d2SLubomir Rintel if (ret)
252725262d2SLubomir Rintel return ret;
253725262d2SLubomir Rintel
254725262d2SLubomir Rintel priv->sspa_mux.hw.init = CLK_HW_INIT_PARENTS_DATA("sspa_mux",
255725262d2SLubomir Rintel sspa_mux_parents, &clk_mux_ops,
256725262d2SLubomir Rintel CLK_SET_RATE_PARENT);
257725262d2SLubomir Rintel priv->sspa_mux.reg = priv->mmio_base + SSPA_AUD_CTRL;
258725262d2SLubomir Rintel priv->sspa_mux.mask = 1;
259725262d2SLubomir Rintel priv->sspa_mux.shift = SSPA_AUD_CTRL_SSPA0_MUX_SHIFT;
260725262d2SLubomir Rintel ret = devm_clk_hw_register(dev, &priv->sspa_mux.hw);
261725262d2SLubomir Rintel if (ret)
262725262d2SLubomir Rintel return ret;
263725262d2SLubomir Rintel
264725262d2SLubomir Rintel priv->sysclk_div.hw.init = CLK_HW_INIT_HW("sys_div",
265725262d2SLubomir Rintel &priv->sspa_mux.hw, &clk_divider_ops,
266725262d2SLubomir Rintel CLK_SET_RATE_PARENT);
267725262d2SLubomir Rintel priv->sysclk_div.reg = priv->mmio_base + SSPA_AUD_CTRL;
268725262d2SLubomir Rintel priv->sysclk_div.shift = SSPA_AUD_CTRL_SYSCLK_DIV_SHIFT;
269725262d2SLubomir Rintel priv->sysclk_div.width = 6;
270725262d2SLubomir Rintel priv->sysclk_div.flags = CLK_DIVIDER_ONE_BASED;
271725262d2SLubomir Rintel priv->sysclk_div.flags |= CLK_DIVIDER_ROUND_CLOSEST;
272725262d2SLubomir Rintel priv->sysclk_div.flags |= CLK_DIVIDER_ALLOW_ZERO;
273725262d2SLubomir Rintel ret = devm_clk_hw_register(dev, &priv->sysclk_div.hw);
274725262d2SLubomir Rintel if (ret)
275725262d2SLubomir Rintel return ret;
276725262d2SLubomir Rintel
277725262d2SLubomir Rintel priv->sysclk_gate.hw.init = CLK_HW_INIT_HW("sys_clk",
278725262d2SLubomir Rintel &priv->sysclk_div.hw, &clk_gate_ops,
279725262d2SLubomir Rintel CLK_SET_RATE_PARENT);
280725262d2SLubomir Rintel priv->sysclk_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;
281725262d2SLubomir Rintel priv->sysclk_gate.bit_idx = SSPA_AUD_CTRL_SYSCLK_SHIFT;
282725262d2SLubomir Rintel ret = devm_clk_hw_register(dev, &priv->sysclk_gate.hw);
283725262d2SLubomir Rintel if (ret)
284725262d2SLubomir Rintel return ret;
285725262d2SLubomir Rintel
286725262d2SLubomir Rintel priv->sspa0_div.hw.init = CLK_HW_INIT_HW("sspa0_div",
287725262d2SLubomir Rintel &priv->sspa_mux.hw, &clk_divider_ops, 0);
288725262d2SLubomir Rintel priv->sspa0_div.reg = priv->mmio_base + SSPA_AUD_CTRL;
289725262d2SLubomir Rintel priv->sspa0_div.shift = SSPA_AUD_CTRL_SSPA0_DIV_SHIFT;
290725262d2SLubomir Rintel priv->sspa0_div.width = 6;
291725262d2SLubomir Rintel priv->sspa0_div.flags = CLK_DIVIDER_ONE_BASED;
292725262d2SLubomir Rintel priv->sspa0_div.flags |= CLK_DIVIDER_ROUND_CLOSEST;
293725262d2SLubomir Rintel priv->sspa0_div.flags |= CLK_DIVIDER_ALLOW_ZERO;
294725262d2SLubomir Rintel ret = devm_clk_hw_register(dev, &priv->sspa0_div.hw);
295725262d2SLubomir Rintel if (ret)
296725262d2SLubomir Rintel return ret;
297725262d2SLubomir Rintel
298725262d2SLubomir Rintel priv->sspa0_gate.hw.init = CLK_HW_INIT_HW("sspa0_clk",
299725262d2SLubomir Rintel &priv->sspa0_div.hw, &clk_gate_ops,
300725262d2SLubomir Rintel CLK_SET_RATE_PARENT);
301725262d2SLubomir Rintel priv->sspa0_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;
302725262d2SLubomir Rintel priv->sspa0_gate.bit_idx = SSPA_AUD_CTRL_SSPA0_SHIFT;
303725262d2SLubomir Rintel ret = devm_clk_hw_register(dev, &priv->sspa0_gate.hw);
304725262d2SLubomir Rintel if (ret)
305725262d2SLubomir Rintel return ret;
306725262d2SLubomir Rintel
307725262d2SLubomir Rintel priv->sspa1_mux.hw.init = CLK_HW_INIT_PARENTS_DATA("sspa1_mux",
308725262d2SLubomir Rintel sspa1_mux_parents, &clk_mux_ops,
309725262d2SLubomir Rintel CLK_SET_RATE_PARENT);
310725262d2SLubomir Rintel priv->sspa1_mux.reg = priv->mmio_base + SSPA_AUD_CTRL;
311725262d2SLubomir Rintel priv->sspa1_mux.mask = 1;
312725262d2SLubomir Rintel priv->sspa1_mux.shift = SSPA_AUD_CTRL_SSPA1_MUX_SHIFT;
313725262d2SLubomir Rintel ret = devm_clk_hw_register(dev, &priv->sspa1_mux.hw);
314725262d2SLubomir Rintel if (ret)
315725262d2SLubomir Rintel return ret;
316725262d2SLubomir Rintel
317725262d2SLubomir Rintel priv->sspa1_div.hw.init = CLK_HW_INIT_HW("sspa1_div",
318725262d2SLubomir Rintel &priv->sspa1_mux.hw, &clk_divider_ops, 0);
319725262d2SLubomir Rintel priv->sspa1_div.reg = priv->mmio_base + SSPA_AUD_CTRL;
320725262d2SLubomir Rintel priv->sspa1_div.shift = SSPA_AUD_CTRL_SSPA1_DIV_SHIFT;
321725262d2SLubomir Rintel priv->sspa1_div.width = 6;
322725262d2SLubomir Rintel priv->sspa1_div.flags = CLK_DIVIDER_ONE_BASED;
323725262d2SLubomir Rintel priv->sspa1_div.flags |= CLK_DIVIDER_ROUND_CLOSEST;
324725262d2SLubomir Rintel priv->sspa1_div.flags |= CLK_DIVIDER_ALLOW_ZERO;
325725262d2SLubomir Rintel ret = devm_clk_hw_register(dev, &priv->sspa1_div.hw);
326725262d2SLubomir Rintel if (ret)
327725262d2SLubomir Rintel return ret;
328725262d2SLubomir Rintel
329725262d2SLubomir Rintel priv->sspa1_gate.hw.init = CLK_HW_INIT_HW("sspa1_clk",
330725262d2SLubomir Rintel &priv->sspa1_div.hw, &clk_gate_ops,
331725262d2SLubomir Rintel CLK_SET_RATE_PARENT);
332725262d2SLubomir Rintel priv->sspa1_gate.reg = priv->mmio_base + SSPA_AUD_CTRL;
333725262d2SLubomir Rintel priv->sspa1_gate.bit_idx = SSPA_AUD_CTRL_SSPA1_SHIFT;
334725262d2SLubomir Rintel ret = devm_clk_hw_register(dev, &priv->sspa1_gate.hw);
335725262d2SLubomir Rintel if (ret)
336725262d2SLubomir Rintel return ret;
337725262d2SLubomir Rintel
338725262d2SLubomir Rintel priv->clk_data.hws[MMP2_CLK_AUDIO_SYSCLK] = &priv->sysclk_gate.hw;
339725262d2SLubomir Rintel priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA0] = &priv->sspa0_gate.hw;
340725262d2SLubomir Rintel priv->clk_data.hws[MMP2_CLK_AUDIO_SSPA1] = &priv->sspa1_gate.hw;
341*46c13513SDuje Mihanović priv->clk_data.num = CLK_AUDIO_NR_CLKS;
342725262d2SLubomir Rintel
343725262d2SLubomir Rintel return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
344725262d2SLubomir Rintel &priv->clk_data);
345725262d2SLubomir Rintel }
346725262d2SLubomir Rintel
mmp2_audio_clk_probe(struct platform_device * pdev)347725262d2SLubomir Rintel static int mmp2_audio_clk_probe(struct platform_device *pdev)
348725262d2SLubomir Rintel {
349725262d2SLubomir Rintel struct mmp2_audio_clk *priv;
350725262d2SLubomir Rintel int ret;
351725262d2SLubomir Rintel
352725262d2SLubomir Rintel priv = devm_kzalloc(&pdev->dev,
353725262d2SLubomir Rintel struct_size(priv, clk_data.hws,
354*46c13513SDuje Mihanović CLK_AUDIO_NR_CLKS),
355725262d2SLubomir Rintel GFP_KERNEL);
356725262d2SLubomir Rintel if (!priv)
357725262d2SLubomir Rintel return -ENOMEM;
358725262d2SLubomir Rintel
359725262d2SLubomir Rintel spin_lock_init(&priv->lock);
360725262d2SLubomir Rintel platform_set_drvdata(pdev, priv);
361725262d2SLubomir Rintel
362725262d2SLubomir Rintel priv->mmio_base = devm_platform_ioremap_resource(pdev, 0);
363725262d2SLubomir Rintel if (IS_ERR(priv->mmio_base))
364725262d2SLubomir Rintel return PTR_ERR(priv->mmio_base);
365725262d2SLubomir Rintel
366725262d2SLubomir Rintel pm_runtime_enable(&pdev->dev);
367725262d2SLubomir Rintel ret = pm_clk_create(&pdev->dev);
368725262d2SLubomir Rintel if (ret)
369725262d2SLubomir Rintel goto disable_pm_runtime;
370725262d2SLubomir Rintel
371725262d2SLubomir Rintel ret = pm_clk_add(&pdev->dev, "audio");
372725262d2SLubomir Rintel if (ret)
373725262d2SLubomir Rintel goto destroy_pm_clk;
374725262d2SLubomir Rintel
375725262d2SLubomir Rintel ret = register_clocks(priv, &pdev->dev);
376725262d2SLubomir Rintel if (ret)
377725262d2SLubomir Rintel goto destroy_pm_clk;
378725262d2SLubomir Rintel
379725262d2SLubomir Rintel return 0;
380725262d2SLubomir Rintel
381725262d2SLubomir Rintel destroy_pm_clk:
382725262d2SLubomir Rintel pm_clk_destroy(&pdev->dev);
383725262d2SLubomir Rintel disable_pm_runtime:
384725262d2SLubomir Rintel pm_runtime_disable(&pdev->dev);
385725262d2SLubomir Rintel
386725262d2SLubomir Rintel return ret;
387725262d2SLubomir Rintel }
388725262d2SLubomir Rintel
mmp2_audio_clk_remove(struct platform_device * pdev)38965ef13feSUwe Kleine-König static void mmp2_audio_clk_remove(struct platform_device *pdev)
390725262d2SLubomir Rintel {
391725262d2SLubomir Rintel pm_clk_destroy(&pdev->dev);
392725262d2SLubomir Rintel pm_runtime_disable(&pdev->dev);
393725262d2SLubomir Rintel }
394725262d2SLubomir Rintel
395c361c5a6SArnd Bergmann #ifdef CONFIG_PM
mmp2_audio_clk_suspend(struct device * dev)396c361c5a6SArnd Bergmann static int mmp2_audio_clk_suspend(struct device *dev)
397725262d2SLubomir Rintel {
398725262d2SLubomir Rintel struct mmp2_audio_clk *priv = dev_get_drvdata(dev);
399725262d2SLubomir Rintel
400725262d2SLubomir Rintel priv->aud_ctrl = readl(priv->mmio_base + SSPA_AUD_CTRL);
401725262d2SLubomir Rintel priv->aud_pll_ctrl0 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL0);
402725262d2SLubomir Rintel priv->aud_pll_ctrl1 = readl(priv->mmio_base + SSPA_AUD_PLL_CTRL1);
403725262d2SLubomir Rintel pm_clk_suspend(dev);
404725262d2SLubomir Rintel
405725262d2SLubomir Rintel return 0;
406725262d2SLubomir Rintel }
407725262d2SLubomir Rintel
mmp2_audio_clk_resume(struct device * dev)408c361c5a6SArnd Bergmann static int mmp2_audio_clk_resume(struct device *dev)
409725262d2SLubomir Rintel {
410725262d2SLubomir Rintel struct mmp2_audio_clk *priv = dev_get_drvdata(dev);
411725262d2SLubomir Rintel
412725262d2SLubomir Rintel pm_clk_resume(dev);
413725262d2SLubomir Rintel writel(priv->aud_ctrl, priv->mmio_base + SSPA_AUD_CTRL);
414725262d2SLubomir Rintel writel(priv->aud_pll_ctrl0, priv->mmio_base + SSPA_AUD_PLL_CTRL0);
415725262d2SLubomir Rintel writel(priv->aud_pll_ctrl1, priv->mmio_base + SSPA_AUD_PLL_CTRL1);
416725262d2SLubomir Rintel
417725262d2SLubomir Rintel return 0;
418725262d2SLubomir Rintel }
419c361c5a6SArnd Bergmann #endif
420725262d2SLubomir Rintel
421725262d2SLubomir Rintel static const struct dev_pm_ops mmp2_audio_clk_pm_ops = {
422725262d2SLubomir Rintel SET_RUNTIME_PM_OPS(mmp2_audio_clk_suspend, mmp2_audio_clk_resume, NULL)
423725262d2SLubomir Rintel };
424725262d2SLubomir Rintel
425725262d2SLubomir Rintel static const struct of_device_id mmp2_audio_clk_of_match[] = {
426725262d2SLubomir Rintel { .compatible = "marvell,mmp2-audio-clock" },
427725262d2SLubomir Rintel {}
428725262d2SLubomir Rintel };
429725262d2SLubomir Rintel
430725262d2SLubomir Rintel MODULE_DEVICE_TABLE(of, mmp2_audio_clk_of_match);
431725262d2SLubomir Rintel
432725262d2SLubomir Rintel static struct platform_driver mmp2_audio_clk_driver = {
433725262d2SLubomir Rintel .driver = {
434725262d2SLubomir Rintel .name = "mmp2-audio-clock",
435725262d2SLubomir Rintel .of_match_table = of_match_ptr(mmp2_audio_clk_of_match),
436725262d2SLubomir Rintel .pm = &mmp2_audio_clk_pm_ops,
437725262d2SLubomir Rintel },
438725262d2SLubomir Rintel .probe = mmp2_audio_clk_probe,
43965ef13feSUwe Kleine-König .remove_new = mmp2_audio_clk_remove,
440725262d2SLubomir Rintel };
441725262d2SLubomir Rintel module_platform_driver(mmp2_audio_clk_driver);
442725262d2SLubomir Rintel
443725262d2SLubomir Rintel MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
444725262d2SLubomir Rintel MODULE_DESCRIPTION("Clock driver for MMP2 Audio subsystem");
445725262d2SLubomir Rintel MODULE_LICENSE("GPL");
446