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Searched refs:mfspr (Results 1 – 25 of 29) sorted by relevance

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/openbmc/u-boot/arch/powerpc/lib/
H A Dbat_rw.c129 l = mfspr (DBAT0L); in read_bat()
130 u = mfspr (DBAT0U); in read_bat()
133 l = mfspr (IBAT0L); in read_bat()
134 u = mfspr (IBAT0U); in read_bat()
137 l = mfspr (DBAT1L); in read_bat()
138 u = mfspr (DBAT1U); in read_bat()
141 l = mfspr (IBAT1L); in read_bat()
142 u = mfspr (IBAT1U); in read_bat()
145 l = mfspr (DBAT2L); in read_bat()
146 u = mfspr (DBAT2U); in read_bat()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Drelease.S30 mfspr r0, MSSCR0
58 mfspr r0, HID0
75 mfspr r3, l2cr
79 mfspr r3, l2cr
88 1: mfspr r3, l2cr
93 mfspr r3, l2cr
100 mfspr r3, HID0
119 mfspr r3, HID0
130 mfspr r4, HID0
137 mfspr r4, HID1
H A Dcache.S36 mfspr r3,HID0
46 mfspr r3,HID0
175 mfspr r3, HID0
193 mfspr r3, HID0
205 mfspr r3, HID0
211 mfspr r3, HID0
227 mfspr r3, HID0
254 mfspr r3, HID0
272 mfspr r3, HID0
280 mfspr r3, l2cr
[all …]
H A Dstart.S87 mfspr r4,DAR
89 mfspr r5,DSISR
866 mfspr r0, HID0
917 mfspr r0, HID0
926 mfspr r0, LDSTCR
953 mfspr r0, HID0
965 mfspr r0, LDSTCR
H A Dtraps.c116 printf("MSS error. MSSSR0: %08x\n", mfspr(SPRN_MSSSR0)); in MachineCheckException()
H A Dcpu.c40 uint msscr0 = mfspr(MSSCR0); in checkcpu()
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Drelease.S32 mfspr r3, SPRN_HDBCR0
48 mfspr r0,PVR
59 mfspr r3,SPRN_HDBCR1
65 mfspr r3,SPRN_SVR
83 mfspr r3,SPRN_HDBCR0
106 mfspr r3,SPRN_L1CSR1
115 mfspr r3,SPRN_L1CSR1
124 mfspr r3,SPRN_L1CSR0
133 mfspr r3,SPRN_L1CSR0
144 mfspr r0,SPRN_PIR
[all …]
H A Dtlb.c52 _mas1 = mfspr(MAS1); in read_tlbcam_entry()
56 *epn = mfspr(MAS2) & MAS2_EPN; in read_tlbcam_entry()
57 *rpn = mfspr(MAS3) & MAS3_RPN; in read_tlbcam_entry()
59 *rpn |= ((u64)mfspr(MAS7)) << 32; in read_tlbcam_entry()
66 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; in print_tlbcam()
102 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; in init_used_tlb_cams()
111 if (mfspr(MAS1) & MAS1_VALID) in init_used_tlb_cams()
145 if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 && in set_tlb()
207 _mas0 = mfspr(MAS0); in find_tlb_idx()
208 _mas1 = mfspr(MAS1); in find_tlb_idx()
[all …]
H A Dstart.S90 mfspr r3,SPRN_SVR
110 mfspr r3,SPRN_HDBCR0
120 mfspr r3, SPRN_HDBCR0
134 mfspr r3, SPRN_L2CSR0
140 mfspr r3, SPRN_L2CSR0
150 mfspr r3, SPRN_L2CSR0
154 mfspr r3, SPRN_L2CSR0
173 mfspr r1,DBSR
315 mfspr r3,PVR
326 mfspr r3,SPRN_HDBCR1
[all …]
H A Dspl_minimal.c41 u32 s = mfspr(SPRN_TBRL); in udelay()
43 while ((mfspr(SPRN_TBRL) - s) < ticks); in udelay()
H A Dtraps.c143 mcsrr0 = mfspr(SPRN_MCSRR0); in MachineCheckException()
144 mcsrr1 = mfspr(SPRN_MCSRR1); in MachineCheckException()
145 mcsr = mfspr(SPRN_MCSR); in MachineCheckException()
146 mcar = mfspr(SPRN_MCAR); in MachineCheckException()
H A Dcpu_init.c681 u32 l2cfg0 = mfspr(SPRN_L2CFG0); in l2cache_init()
685 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) in l2cache_init()
697 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) in l2cache_init()
774 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); in cpu_init_r()
781 mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID)); in cpu_init_r()
790 if (mfspr(L1CSR2) & L1CSR2_DCWS) in cpu_init_r()
791 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); in cpu_init_r()
H A Dinterrupts.c44 mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE); in interrupt_init_cpu()
H A Dfdt.c295 u32 l2cfg0 = mfspr(SPRN_L2CFG0); in ft_fixup_l2cache()
388 u32 l1cfg0 = mfspr(SPRN_L1CFG0); in ft_fixup_cache()
389 u32 l1cfg1 = mfspr(SPRN_L1CFG1); in ft_fixup_cache()
493 svr = mfspr(SPRN_SVR); in ft_fixup_qe_snum()
H A Dcpu.c308 val = mfspr(DBCR0); in do_reset()
345 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) | in init_85xx_watchdog()
H A Dmp.c23 return mfspr(SPRN_PIR); in get_my_id()
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dppc.h44 return mfspr(SPRN_IMMR); in get_immr()
49 return mfspr(PVR); in get_pvr()
54 return mfspr(SVR); in get_svr()
H A Dcache.h114 return mfspr(IC_CST); in rd_ic_cst()
129 return mfspr(DC_CST); in rd_dc_cst()
/openbmc/openbmc/poky/meta/recipes-devtools/valgrind/valgrind/
H A DAdded-support-for-PPC-instructions-mfatbu-mfatbl.patch7 dis_proc_ctl(ppc)(mfspr,SPR)(0x20F)
47 + __asm__ __volatile__("mfspr %0,527" : "=b"(spr));
49 + __asm__ __volatile__("mfspr %0,526" : "=b"(spr));
87 + DIP("mfspr r%u,%u", rD_addr, (UInt)SPR);
92 vex_printf("dis_proc_ctl(ppc)(mfspr,SPR)(0x%x)\n", SPR);
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dcache.c15 return !!(mfspr(IC_CST) & IDC_ENABLED); in icache_status()
33 return !!(mfspr(IC_CST) & IDC_ENABLED); in dcache_status()
H A Dstart.S81 mfspr r3, ICR /* clear Interrupt Cause Register */
94 mfspr r3, IC_CST /* Clear error bits */
95 mfspr r3, DC_CST
202 mfspr r4,DAR
204 mfspr r5,DSISR
/openbmc/u-boot/include/
H A Dppc_asm.tmpl172 mfspr r20,SPRG0; \
174 mfspr r22,SPRG1; \
180 mfspr r20,XER; \
182 mfspr r20, DAR_DEAR; \
184 mfspr r22,reg1; \
185 mfspr r23,reg2; \
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dstart.S332 mfspr r4,DAR
334 mfspr r5,DSISR
741 mfspr r3, HID0
754 mfspr r3, HID0
764 mfspr r3, HID0
771 mfspr r3, HID0
783 mfspr r3, HID0
796 mfspr r3, HID0
1081 mfspr r0, HID0
1105 mfspr r3, HID0
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-dbs/rocksdb/files/
H A D0004-Implement-support-for-musl-ppc64.patch35 + asm volatile("mfspr %0, 268" : "=r"(result));
/openbmc/u-boot/board/keymile/km83xx/
H A Dkm83xx.c157 svid = SVR_REV(mfspr(SVR)); in board_early_init_r()

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