1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2b9735cbaSScott Wood /* 3b9735cbaSScott Wood * Copyright 2009 Freescale Semiconductor, Inc. 4b9735cbaSScott Wood */ 5b9735cbaSScott Wood 6b9735cbaSScott Wood #include <common.h> 7b9735cbaSScott Wood #include <asm/processor.h> 8b9735cbaSScott Wood #include <asm/global_data.h> 90b66513bSYork Sun #include <fsl_ifc.h> 10b9735cbaSScott Wood #include <asm/io.h> 11b9735cbaSScott Wood 12b9735cbaSScott Wood DECLARE_GLOBAL_DATA_PTR; 13b9735cbaSScott Wood cpu_init_f(void)14701e6401SYork Sunulong cpu_init_f(void) 15b9735cbaSScott Wood { 16c97cd1baSScott Wood #ifdef CONFIG_SYS_INIT_L2_ADDR 17b9735cbaSScott Wood ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; 18b9735cbaSScott Wood 19b9735cbaSScott Wood out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR); 20b9735cbaSScott Wood 21b9735cbaSScott Wood /* set MBECCDIS=1, SBECCDIS=1 */ 22b9735cbaSScott Wood out_be32(&l2cache->l2errdis, 23b9735cbaSScott Wood (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC)); 24b9735cbaSScott Wood 25b9735cbaSScott Wood /* set L2E=1 & L2SRAM=001 */ 26b9735cbaSScott Wood out_be32(&l2cache->l2ctl, 27b9735cbaSScott Wood (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); 28b9735cbaSScott Wood #endif 29701e6401SYork Sun 30701e6401SYork Sun return 0; 31b9735cbaSScott Wood } 32b9735cbaSScott Wood 33b9735cbaSScott Wood #ifndef CONFIG_SYS_FSL_TBCLK_DIV 34b9735cbaSScott Wood #define CONFIG_SYS_FSL_TBCLK_DIV 8 35b9735cbaSScott Wood #endif 36b9735cbaSScott Wood udelay(unsigned long usec)37b9735cbaSScott Woodvoid udelay(unsigned long usec) 38b9735cbaSScott Wood { 39b9735cbaSScott Wood u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000); 40b9735cbaSScott Wood u32 ticks = ticks_per_usec * usec; 41b9735cbaSScott Wood u32 s = mfspr(SPRN_TBRL); 42b9735cbaSScott Wood 43b9735cbaSScott Wood while ((mfspr(SPRN_TBRL) - s) < ticks); 44b9735cbaSScott Wood } 45