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Searched refs:mctl_com (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a23.c226 setbits_le32(&mctl_com->ccr, 0x80000); in mctl_init()
287 &mctl_com->cr); in sunxi_dram_init()
302 &mctl_com->cr); in sunxi_dram_init()
307 writel(0x00000008, &mctl_com->mcr0_0); in sunxi_dram_init()
308 writel(0x0001000d, &mctl_com->mcr1_0); in sunxi_dram_init()
309 writel(0x00000004, &mctl_com->mcr0_1); in sunxi_dram_init()
310 writel(0x00000080, &mctl_com->mcr1_1); in sunxi_dram_init()
311 writel(0x00000004, &mctl_com->mcr0_2); in sunxi_dram_init()
312 writel(0x00000019, &mctl_com->mcr1_2); in sunxi_dram_init()
313 writel(0x00000004, &mctl_com->mcr0_3); in sunxi_dram_init()
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H A Ddram_sun6i.c304 writel(0x00400302, &mctl_com->rmcr[0]); in mctl_port_cfg()
305 writel(0x01000307, &mctl_com->rmcr[1]); in mctl_port_cfg()
306 writel(0x00400302, &mctl_com->rmcr[2]); in mctl_port_cfg()
307 writel(0x01000307, &mctl_com->rmcr[3]); in mctl_port_cfg()
308 writel(0x01000307, &mctl_com->rmcr[4]); in mctl_port_cfg()
309 writel(0x01000303, &mctl_com->rmcr[6]); in mctl_port_cfg()
310 writel(0x01000303, &mctl_com->mmcr[0]); in mctl_port_cfg()
311 writel(0x00400310, &mctl_com->mmcr[1]); in mctl_port_cfg()
312 writel(0x01000307, &mctl_com->mmcr[2]); in mctl_port_cfg()
371 clrsetbits_le32(&mctl_com->cr, in sunxi_dram_init()
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H A Ddram_sunxi_dw.c101 writel(cfg0, &mctl_com->mcr[port][0]); in mbus_configure_port()
118 writel(0x00000001, &mctl_com->mapr); in mctl_set_master_priority_h3()
140 writel(399, &mctl_com->tmr); in mctl_set_master_priority_a64()
141 writel((1 << 16), &mctl_com->bwcr); in mctl_set_master_priority_a64()
167 writel(399, &mctl_com->tmr); in mctl_set_master_priority_h5()
168 writel((1 << 16), &mctl_com->bwcr); in mctl_set_master_priority_h5()
171 writel(0x00000001, &mctl_com->mapr); in mctl_set_master_priority_h5()
195 writel(399, &mctl_com->tmr); in mctl_set_master_priority_r40()
196 writel((1 << 16), &mctl_com->bwcr); in mctl_set_master_priority_r40()
199 writel(0x00000001, &mctl_com->mapr); in mctl_set_master_priority_r40()
[all …]
H A Ddram_sun50i_h6.c150 writel(399, &mctl_com->tmr); in mctl_set_master_priority()
151 writel(BIT(16), &mctl_com->bwcr); in mctl_set_master_priority()
323 writel(0, &mctl_com->maer0); in mctl_sys_init()
324 writel(0, &mctl_com->maer1); in mctl_sys_init()
325 writel(0, &mctl_com->maer2); in mctl_sys_init()
428 setbits_le32(&mctl_com->cr, BIT(31)); in mctl_com_init()
435 clrbits_le32(&mctl_com->cr, BIT(27)); in mctl_com_init()
437 setbits_le32(&mctl_com->cr, BIT(27)); in mctl_com_init()
673 writel(0xffffffff, &mctl_com->maer0); in mctl_channel_init()
674 writel(0x7ff, &mctl_com->maer1); in mctl_channel_init()
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H A Ddram_sun8i_a33.c34 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr() local
43 &mctl_com->cr); in mctl_set_cr()
205 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init() local
289 writel(0xffffffff, &mctl_com->maer); in mctl_channel_init()
300 struct sunxi_mctl_com_reg * const mctl_com = in mctl_sys_init() local
320 writel(0x0, &mctl_com->mapr); in mctl_sys_init()
329 struct sunxi_mctl_com_reg * const mctl_com = in sunxi_dram_init() local
351 writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr); in sunxi_dram_init()
H A Ddram_sun9i.c202 struct sunxi_mctl_com_reg * const mctl_com = in mctl_sys_init() local
300 setbits_le32(&mctl_com->ccr, (1 << 14) | (1 << 30)); in mctl_sys_init()
333 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN); in mctl_sys_init()
335 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); in mctl_sys_init()
340 struct sunxi_mctl_com_reg * const mctl_com = in mctl_com_init() local
350 &mctl_com->cr); in mctl_com_init()
352 debug("CR: %d\n", readl(&mctl_com->cr)); in mctl_com_init()
825 struct sunxi_mctl_com_reg * const mctl_com = in DRAMC_get_dram_size() local
832 reg_val = readl(&mctl_com->cr); in DRAMC_get_dram_size()
856 struct sunxi_mctl_com_reg * const mctl_com = in sunxi_dram_init() local
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H A Ddram_sun8i_a83t.c33 struct sunxi_mctl_com_reg * const mctl_com = in mctl_set_cr() local
42 &mctl_com->cr); in mctl_set_cr()
261 struct sunxi_mctl_com_reg * const mctl_com = in mctl_channel_init() local
270 writel(0x000101a0, &mctl_com->bwcr); in mctl_channel_init()
272 writel(0x1, &mctl_com->mapr); in mctl_channel_init()
326 if (readl(&mctl_com->cr) & 0x1) in mctl_channel_init()
383 writel(0xffffffff, &mctl_com->maer); in mctl_channel_init()
427 struct sunxi_mctl_com_reg * const mctl_com = in sunxi_dram_init() local
461 writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr); in sunxi_dram_init()