202 	struct sunxi_mctl_com_reg * const mctl_com =  in mctl_sys_init()  local
300 	setbits_le32(&mctl_com->ccr, (1 << 14) | (1 << 30));  in mctl_sys_init()
301 	writel(2, &mctl_com->rmcr); /* controller clock is PLL6/4 */  in mctl_sys_init()
330 	clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN | MCTL_CCR_CH1_CLK_EN);  in mctl_sys_init()
333 	setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN);  in mctl_sys_init()
335 	setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);  in mctl_sys_init()
340 	struct sunxi_mctl_com_reg * const mctl_com =  in mctl_com_init()  local
350 	       &mctl_com->cr);  in mctl_com_init()
352 	debug("CR: %d\n", readl(&mctl_com->cr));  in mctl_com_init()
825 	struct sunxi_mctl_com_reg * const mctl_com =  in DRAMC_get_dram_size()  local
832 	reg_val = readl(&mctl_com->cr);  in DRAMC_get_dram_size()
856 	struct sunxi_mctl_com_reg * const mctl_com =  in sunxi_dram_init()  local
948 		clrsetbits_le32(&mctl_com->cr, MCTL_CR_CHANNEL_MASK,  in sunxi_dram_init()
951 		clrbits_le32(&mctl_com->cr, MCTL_CCR_CH1_CLK_EN);  in sunxi_dram_init()