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Searched refs:max_clk (Results 1 – 25 of 42) sorted by relevance

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/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dsys_info.c269 max_clk = "720 MHz"; in print_cpuinfo()
271 max_clk = "600 MHz"; in print_cpuinfo()
287 max_clk = "600 MHz"; in print_cpuinfo()
294 max_clk = "800 MHz"; in print_cpuinfo()
299 max_clk = "1 GHz"; in print_cpuinfo()
304 max_clk = "800 MHz"; in print_cpuinfo()
309 max_clk = "1 GHz"; in print_cpuinfo()
319 max_clk = "1 GHz"; in print_cpuinfo()
329 max_clk = "1 GHz"; in print_cpuinfo()
334 max_clk = "1 GHz"; in print_cpuinfo()
[all …]
/openbmc/u-boot/drivers/mmc/
H A Datmel_sdhci.c21 u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ; in atmel_sdhci_init() local
32 max_clk = at91_get_periph_generated_clk(id); in atmel_sdhci_init()
33 if (!max_clk) { in atmel_sdhci_init()
38 host->max_clk = max_clk; in atmel_sdhci_init()
59 u32 max_clk; in atmel_sdhci_probe() local
86 max_clk = clk_get_rate(&clk); in atmel_sdhci_probe()
87 if (!max_clk) in atmel_sdhci_probe()
90 host->max_clk = max_clk; in atmel_sdhci_probe()
H A Dkona_sdhci.c80 u32 max_clk; in kona_sdhci_init() local
93 &max_clk); in kona_sdhci_init()
98 &max_clk); in kona_sdhci_init()
103 &max_clk); in kona_sdhci_init()
108 &max_clk); in kona_sdhci_init()
123 host->max_clk = max_clk; in kona_sdhci_init()
H A Dsdhci.c363 if ((host->max_clk / div) <= clock)
375 if (host->max_clk <= clock) {
381 if ((host->max_clk / div) <= clock)
390 if ((host->max_clk / div) <= clock)
620 if (host->max_clk == 0) {
625 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
627 host->max_clk *= 1000000;
629 host->max_clk *= host->clk_mul;
631 if (host->max_clk == 0) {
636 if (f_max && (f_max < host->max_clk))
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H A Dmv_sdhci.c67 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) in mv_sdh_init() argument
79 host->max_clk = max_clk; in mv_sdh_init()
H A Dbcm2835_sdhost.c164 unsigned int max_clk; /* Max possible freq */ member
626 div = host->max_clk / clock; in bcm2835_set_clock()
629 if ((host->max_clk / div) > clock) in bcm2835_set_clock()
636 clock = host->max_clk / (div + 2); in bcm2835_set_clock()
731 cfg->f_max = host->max_clk; in bcm2835_add_host()
732 cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV; in bcm2835_add_host()
771 host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE); in bcm2835_probe()
H A Ddw_mmc.c541 u32 max_clk, u32 min_clk) argument
548 cfg->f_max = max_clk;
572 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk) argument
574 dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
H A Dpic32_sdhci.c58 host->max_clk = f_min_max[1]; in pic32_sdhci_probe()
H A Dk3_arsan_sdhci.c60 host->max_clk = clock; in k3_arasan_sdhci_probe()
H A Drockchip_sdhci.c62 host->max_clk = max_frequency; in arasan_sdhci_probe()
H A Daspeed_sdhci.c85 host->max_clk = clock; in aspeed_sdhci_probe()
H A Dmsm_sdhci.c98 host->max_clk = 0; in msm_sdc_probe()
/openbmc/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.c103 .max_clk = 200000000,
184 .max_clk = 200000000,
271 .max_clk = 320000000,
371 .max_clk = 320000000,
443 .max_clk = 320000000,
523 .max_clk = 366670000,
623 .max_clk = 400000000,
736 .max_clk = 412500000,
833 .max_clk = 360000000,
926 .max_clk = 400000000,
[all …]
H A Dmdp5_cfg.h104 uint32_t max_clk; member
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-of-esdhc.c36 const unsigned int max_clk[MMC_TIMING_NUM]; member
41 .max_clk[MMC_TIMING_MMC_HS] = 46500000,
42 .max_clk[MMC_TIMING_SD_HS] = 46500000,
47 .max_clk[MMC_TIMING_UHS_SDR104] = 116700000,
48 .max_clk[MMC_TIMING_MMC_HS200] = 116700000,
53 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000,
54 .max_clk[MMC_TIMING_MMC_HS200] = 167000000,
60 .max_clk[MMC_TIMING_MMC_HS200] = 125000000,
65 .max_clk[MMC_TIMING_LEGACY] = 20000000,
66 .max_clk[MMC_TIMING_MMC_HS] = 42000000,
[all …]
H A Dbcm2835.c154 unsigned int max_clk; /* Max possible freq */ member
1127 div = host->max_clk / clock; in bcm2835_set_clock()
1130 if ((host->max_clk / div) > clock) in bcm2835_set_clock()
1137 clock = host->max_clk / (div + 2); in bcm2835_set_clock()
1264 if (!mmc->f_max || mmc->f_max > host->max_clk) in bcm2835_add_host()
1265 mmc->f_max = host->max_clk; in bcm2835_add_host()
1266 mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV; in bcm2835_add_host()
1403 host->max_clk = clk_get_rate(clk); in bcm2835_probe()
H A Dsdhci.c1942 if (host->max_clk <= clock) in sdhci_calc_clk()
1947 if ((host->max_clk / div) <= clock) in sdhci_calc_clk()
1954 && !div && host->max_clk <= 25000000) in sdhci_calc_clk()
1960 if ((host->max_clk / div) <= clock) in sdhci_calc_clk()
4234 u32 max_clk; in sdhci_setup_host() local
4391 host->max_clk *= 1000000; in sdhci_setup_host()
4392 if (host->max_clk == 0 || host->quirks & in sdhci_setup_host()
4421 max_clk = host->max_clk; in sdhci_setup_host()
4427 max_clk = host->max_clk * host->clk_mul; in sdhci_setup_host()
4436 if (!mmc->f_max || mmc->f_max > max_clk) in sdhci_setup_host()
[all …]
/openbmc/u-boot/include/
H A Ddwmmc.h270 u32 max_clk, u32 min_clk);
300 int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk);
/openbmc/linux/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4_kms.c389 unsigned long max_clk; in mdp4_kms_init() local
392 max_clk = 266667000; in mdp4_kms_init()
459 clk_set_rate(mdp4_kms->clk, max_clk); in mdp4_kms_init()
479 clk_set_rate(mdp4_kms->lut_clk, max_clk); in mdp4_kms_init()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_6_ppt.c795 uint32_t min_clk, max_clk; in smu_v13_0_6_print_clk_levels() local
820 max_clk = pstate_table->gfxclk_pstate.curr.max; in smu_v13_0_6_print_clk_levels()
829 max_clk); in smu_v13_0_6_print_clk_levels()
835 max_clk, in smu_v13_0_6_print_clk_levels()
1485 uint32_t max_clk; in smu_v13_0_6_set_soft_freq_limited_range() local
1527 max_clk = dpm_context->dpm_tables.gfx_table.max; in smu_v13_0_6_set_soft_freq_limited_range()
1529 max_clk); in smu_v13_0_6_set_soft_freq_limited_range()
1556 uint32_t max_clk; in smu_v13_0_6_usr_edit_dpm_table() local
1610 max_clk = dpm_context->dpm_tables.gfx_table.max; in smu_v13_0_6_usr_edit_dpm_table()
1613 smu, SMU_GFXCLK, min_clk, max_clk); in smu_v13_0_6_usr_edit_dpm_table()
[all …]
H A Daldebaran_ppt.c754 uint32_t min_clk, max_clk; in aldebaran_print_clk_levels() local
787 max_clk = pstate_table->gfxclk_pstate.curr.max; in aldebaran_print_clk_levels()
790 freq_values[1] = max_clk; in aldebaran_print_clk_levels()
793 if (now > min_clk && now < max_clk) { in aldebaran_print_clk_levels()
795 freq_values[2] = max_clk; in aldebaran_print_clk_levels()
1311 uint32_t max_clk; in aldebaran_set_soft_freq_limited_range() local
1352 max_clk = dpm_context->dpm_tables.gfx_table.max; in aldebaran_set_soft_freq_limited_range()
1353 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk); in aldebaran_set_soft_freq_limited_range()
1379 uint32_t max_clk; in aldebaran_usr_edit_dpm_table() local
1425 max_clk = dpm_context->dpm_tables.gfx_table.max; in aldebaran_usr_edit_dpm_table()
[all …]
H A Dsmu_v13_0_5_ppt.c836 uint32_t max_clk = max; in smu_v13_0_5_set_soft_freq_limited_range() local
859 max_clk = max << SMU_13_VCLK_SHIFT; in smu_v13_0_5_set_soft_freq_limited_range()
866 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL); in smu_v13_0_5_set_soft_freq_limited_range()
986 uint32_t *max_clk) in smu_v13_0_5_get_dpm_profile_freq() argument
1010 *min_clk = *max_clk = clk_limit; in smu_v13_0_5_get_dpm_profile_freq()
H A Dsmu_v13_0_4_ppt.c860 uint32_t max_clk = max; in smu_v13_0_4_set_soft_freq_limited_range() local
891 max_clk = max << SMU_13_VCLK_SHIFT; in smu_v13_0_4_set_soft_freq_limited_range()
899 max_clk, NULL); in smu_v13_0_4_set_soft_freq_limited_range()
940 uint32_t *max_clk) in smu_v13_0_4_get_dpm_profile_freq() argument
976 *min_clk = *max_clk = clk_limit; in smu_v13_0_4_get_dpm_profile_freq()
H A Dyellow_carp_ppt.c970 uint32_t max_clk = max; in yellow_carp_set_soft_freq_limited_range() local
1002 max_clk = max << SMU_13_VCLK_SHIFT; in yellow_carp_set_soft_freq_limited_range()
1010 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL); in yellow_carp_set_soft_freq_limited_range()
1170 uint32_t *max_clk) in yellow_carp_get_dpm_profile_freq() argument
1205 *min_clk = *max_clk = clk_limit; in yellow_carp_get_dpm_profile_freq()
/openbmc/u-boot/arch/arm/mach-mvebu/include/mach/
H A Dcpu.h144 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);

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