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Searched refs:ioaddr (Results 1 – 25 of 54) sorted by relevance

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/openbmc/qemu/include/qemu/
H A Dhost-pci-mmio.h16 static inline uint8_t host_pci_ldub_p(const void *ioaddr) in host_pci_ldub_p() argument
20 ret = s390x_pci_mmio_read_8(ioaddr); in host_pci_ldub_p()
22 ret = ldub_p(ioaddr); in host_pci_ldub_p()
28 static inline uint16_t host_pci_lduw_le_p(const void *ioaddr) in host_pci_lduw_le_p() argument
32 ret = le16_to_cpu(s390x_pci_mmio_read_16(ioaddr)); in host_pci_lduw_le_p()
34 ret = lduw_le_p(ioaddr); in host_pci_lduw_le_p()
40 static inline uint32_t host_pci_ldl_le_p(const void *ioaddr) in host_pci_ldl_le_p() argument
44 ret = le32_to_cpu(s390x_pci_mmio_read_32(ioaddr)); in host_pci_ldl_le_p()
46 ret = ldl_le_p(ioaddr); in host_pci_ldl_le_p()
52 static inline uint64_t host_pci_ldq_le_p(const void *ioaddr) in host_pci_ldq_le_p() argument
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H A Ds390x_pci_mmio.h13 uint8_t s390x_pci_mmio_read_8(const void *ioaddr);
14 uint16_t s390x_pci_mmio_read_16(const void *ioaddr);
15 uint32_t s390x_pci_mmio_read_32(const void *ioaddr);
16 uint64_t s390x_pci_mmio_read_64(const void *ioaddr);
18 void s390x_pci_mmio_write_8(void *ioaddr, uint8_t val);
19 void s390x_pci_mmio_write_16(void *ioaddr, uint16_t val);
20 void s390x_pci_mmio_write_32(void *ioaddr, uint32_t val);
21 void s390x_pci_mmio_write_64(void *ioaddr, uint64_t val);
/openbmc/qemu/util/
H A Ds390x_pci_mmio.c30 static uint64_t s390x_pcilgi(const void *ioaddr, size_t len) in s390x_pcilgi() argument
32 union register_pair ioaddr_len = { .even = (uint64_t)ioaddr, in s390x_pcilgi()
52 static void s390x_pcistgi(void *ioaddr, uint64_t val, size_t len) in s390x_pcistgi() argument
54 union register_pair ioaddr_len = {.even = (uint64_t)ioaddr, .odd = len}; in s390x_pcistgi()
64 uint8_t s390x_pci_mmio_read_8(const void *ioaddr) in s390x_pci_mmio_read_8() argument
69 val = s390x_pcilgi(ioaddr, sizeof(val)); in s390x_pci_mmio_read_8()
71 syscall(__NR_s390_pci_mmio_read, ioaddr, &val, sizeof(val)); in s390x_pci_mmio_read_8()
76 uint16_t s390x_pci_mmio_read_16(const void *ioaddr) in s390x_pci_mmio_read_16() argument
81 val = s390x_pcilgi(ioaddr, sizeof(val)); in s390x_pci_mmio_read_16()
83 syscall(__NR_s390_pci_mmio_read, ioaddr, &val, sizeof(val)); in s390x_pci_mmio_read_16()
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/openbmc/u-boot/drivers/ata/
H A Dsata_sil3114.c32 static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
34 static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus);
41 static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words) in output_data() argument
44 __raw_writew (*sect_buf++, (void *)ioaddr->data_addr); in output_data()
48 static int input_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words) in input_data() argument
51 *sect_buf++ = __raw_readw ((void *)ioaddr->data_addr); in input_data()
63 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); in sata_bus_softreset()
65 writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr); in sata_bus_softreset()
67 writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); in sata_bus_softreset()
78 status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0); in sata_bus_softreset()
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/openbmc/u-boot/drivers/net/
H A Duli526x.c80 #define SROM_CLK_WRITE(data, ioaddr) do { \ argument
81 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
83 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
85 outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
107 long ioaddr; /* I/O base address */ member
241 db->ioaddr = dev->iobase; in uli526x_initialize()
294 __FUNCTION__, db->ioaddr); in uli526x_init_one()
309 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, in uli526x_init_one()
342 if (!((inl(db->ioaddr + DCR12)) & 0x8)) { in uli526x_disable()
344 outl(ULI526X_RESET, db->ioaddr + DCR0); in uli526x_disable()
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H A Drtl8139.c173 static int ioaddr; variable
250 ioaddr = dev->iobase; in rtl8139_probe()
253 outb(0x00, ioaddr + Config1); in rtl8139_probe()
261 if (inb(ioaddr + MediaStatus) & MSRLinkFail) { in rtl8139_probe()
296 long ee_addr = ioaddr + Cfg9346; in read_eeprom()
340 outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig); in set_rx_mode()
342 outl(mc_filter[0], ioaddr + MAR0 + 0); in set_rx_mode()
343 outl(mc_filter[1], ioaddr + MAR0 + 4); in set_rx_mode()
350 outb(CmdReset, ioaddr + ChipCmd); in rtl_reset()
357 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break; in rtl_reset()
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H A Ddc2114x.c145 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len);
146 static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len);
149 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
153 static int read_srom(struct eth_device *dev, u_long ioaddr, int index);
544 static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len) in do_read_eeprom() argument
550 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr); in do_read_eeprom()
551 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr); in do_read_eeprom()
560 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr); in do_read_eeprom()
562 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr); in do_read_eeprom()
565 printf("%X", getfrom_srom(dev, ioaddr) & 15); in do_read_eeprom()
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H A Drtl8169.c61 static unsigned long ioaddr; variable
98 #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg))
99 #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg))
100 #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg))
101 #define RTL_R8(reg) readb(ioaddr + (reg))
102 #define RTL_R16(reg) readw(ioaddr + (reg))
103 #define RTL_R32(reg) readl(ioaddr + (reg))
391 ioaddr = dev_iobase; in rtl8169_init_board()
525 ioaddr = dev_iobase; in rtl_recv_common()
619 ioaddr = dev_iobase; in rtl_send_common()
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H A Dpic32_mdio.c103 int pic32_mdio_init(const char *name, ulong ioaddr) in pic32_mdio_init() argument
117 bus->priv = (void *)ioaddr; in pic32_mdio_init()
/openbmc/u-boot/drivers/mmc/
H A Dbcm2835_sdhost.c160 void __iomem *ioaddr; member
185 dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD)); in bcm2835_dumpregs()
186 dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG)); in bcm2835_dumpregs()
187 dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT)); in bcm2835_dumpregs()
188 dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV)); in bcm2835_dumpregs()
189 dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0)); in bcm2835_dumpregs()
190 dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1)); in bcm2835_dumpregs()
191 dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2)); in bcm2835_dumpregs()
192 dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3)); in bcm2835_dumpregs()
193 dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS)); in bcm2835_dumpregs()
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H A Dsti_sdhci.c51 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_1); in sti_mmc_core_config()
55 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_2); in sti_mmc_core_config()
57 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_3); in sti_mmc_core_config()
60 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_2); in sti_mmc_core_config()
62 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_3); in sti_mmc_core_config()
65 host->ioaddr + FLASHSS_MMC_CORE_CONFIG_4); in sti_mmc_core_config()
118 host->ioaddr = (void *)devfdt_get_addr(dev); in sti_sdhci_ofdata_to_platdata()
H A Dtangier_sdhci.c20 void __iomem *ioaddr; member
42 plat->ioaddr = devm_ioremap(dev, base, SZ_1K); in sdhci_tangier_probe()
43 if (!plat->ioaddr) in sdhci_tangier_probe()
47 host->ioaddr = plat->ioaddr; in sdhci_tangier_probe()
H A Dmv_sdhci.c49 u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2; in mv_sdhci_writeb()
58 writeb(val, host->ioaddr + reg); in mv_sdhci_writeb()
77 host->ioaddr = (void *)regbase; in mv_sdh_init()
H A Dmsm_sdhci.c139 caps = readl(host->ioaddr + SDHCI_CAPABILITIES); in msm_sdc_probe()
141 writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0); in msm_sdc_probe()
173 host->ioaddr = (void *)devfdt_get_addr(dev); in msm_ofdata_to_platdata()
179 host->ioaddr == (void *)FDT_ADDR_T_NONE) in msm_ofdata_to_platdata()
H A Dbcm2835_sdhci.c88 writel(val, host->ioaddr + reg); in bcm2835_sdhci_raw_writel()
94 return readl(host->ioaddr + reg); in bcm2835_sdhci_raw_readl()
210 host->ioaddr = (void *)base; in bcm2835_sdhci_probe()
H A Drockchip_sdhci.c46 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); in arasan_sdhci_probe()
89 host->ioaddr = dev_read_addr_ptr(dev); in arasan_sdhci_ofdata_to_platdata()
H A Datmel_sdhci.c30 host->ioaddr = regbase; in atmel_sdhci_init()
72 host->ioaddr = (void *)devfdt_get_addr(dev); in atmel_sdhci_probe()
H A Dftsdc010_mci.h22 void *ioaddr; member
/openbmc/u-boot/drivers/virtio/
H A Dvirtio_pci_legacy.c95 void __iomem *ioaddr; member
102 void __iomem *ioaddr = priv->ioaddr + VIRTIO_PCI_CONFIG_OFF(false); in virtio_pci_get_config() local
107 ptr[i] = ioread8(ioaddr + i); in virtio_pci_get_config()
116 void __iomem *ioaddr = priv->ioaddr + VIRTIO_PCI_CONFIG_OFF(false); in virtio_pci_set_config() local
121 iowrite8(ptr[i], ioaddr + i); in virtio_pci_set_config()
130 *status = ioread8(priv->ioaddr + VIRTIO_PCI_STATUS); in virtio_pci_get_status()
142 iowrite8(status, priv->ioaddr + VIRTIO_PCI_STATUS); in virtio_pci_set_status()
152 iowrite8(0, priv->ioaddr + VIRTIO_PCI_STATUS); in virtio_pci_reset()
158 ioread8(priv->ioaddr + VIRTIO_PCI_STATUS); in virtio_pci_reset()
171 *features = ioread32(priv->ioaddr + VIRTIO_PCI_HOST_FEATURES); in virtio_pci_get_features()
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/openbmc/u-boot/drivers/video/meson/
H A Dmeson_dw_hdmi.c66 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_read()
67 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_read()
70 data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG); in dw_hdmi_top_read()
71 data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG); in dw_hdmi_top_read()
80 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_write()
81 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG); in dw_hdmi_top_write()
84 writel(data, hdmi->ioaddr + HDMITX_TOP_DATA_REG); in dw_hdmi_top_write()
104 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_read()
105 writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG); in dw_hdmi_dwc_read()
108 data = readl(hdmi->ioaddr + HDMITX_DWC_DATA_REG); in dw_hdmi_dwc_read()
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/openbmc/u-boot/include/
H A Dsdhci.h261 void *ioaddr; member
289 writel(val, host->ioaddr + reg); in sdhci_writel()
297 writew(val, host->ioaddr + reg); in sdhci_writew()
305 writeb(val, host->ioaddr + reg); in sdhci_writeb()
313 return readl(host->ioaddr + reg); in sdhci_readl()
321 return readw(host->ioaddr + reg); in sdhci_readw()
329 return readb(host->ioaddr + reg); in sdhci_readb()
336 writel(val, host->ioaddr + reg); in sdhci_writel()
341 writew(val, host->ioaddr + reg); in sdhci_writew()
346 writeb(val, host->ioaddr + reg); in sdhci_writeb()
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H A Ddwmmc.h161 void *ioaddr; member
209 writel(val, host->ioaddr + reg); in dwmci_writel()
214 writew(val, host->ioaddr + reg); in dwmci_writew()
219 writeb(val, host->ioaddr + reg); in dwmci_writeb()
223 return readl(host->ioaddr + reg); in dwmci_readl()
228 return readw(host->ioaddr + reg); in dwmci_readw()
233 return readb(host->ioaddr + reg); in dwmci_readb()
/openbmc/qemu/hw/pci-host/
H A Ddino.c101 uint16_t ioaddr; in dino_chip_read_with_attrs() local
108 ioaddr = phb->config_reg + (addr & 3); in dino_chip_read_with_attrs()
111 val = address_space_ldub(io, ioaddr, attrs, &ret); in dino_chip_read_with_attrs()
114 val = address_space_lduw_be(io, ioaddr, attrs, &ret); in dino_chip_read_with_attrs()
117 val = address_space_ldl_be(io, ioaddr, attrs, &ret); in dino_chip_read_with_attrs()
194 uint16_t ioaddr; in dino_chip_write_with_attrs() local
203 ioaddr = phb->config_reg + (addr & 3); in dino_chip_write_with_attrs()
206 address_space_stb(io, ioaddr, val, attrs, &ret); in dino_chip_write_with_attrs()
209 address_space_stw_be(io, ioaddr, val, attrs, &ret); in dino_chip_write_with_attrs()
212 address_space_stl_be(io, ioaddr, val, attrs, &ret); in dino_chip_write_with_attrs()
/openbmc/qemu/hw/net/
H A Digb.c78 uint32_t ioaddr; member
138 if (s->ioaddr < 0x1FFFF) { in igb_io_get_reg_index()
139 *idx = s->ioaddr; in igb_io_get_reg_index()
143 if (s->ioaddr < 0x7FFFF) { in igb_io_get_reg_index()
144 trace_e1000e_wrn_io_addr_undefined(s->ioaddr); in igb_io_get_reg_index()
148 if (s->ioaddr < 0xFFFFF) { in igb_io_get_reg_index()
149 trace_e1000e_wrn_io_addr_flash(s->ioaddr); in igb_io_get_reg_index()
153 trace_e1000e_wrn_io_addr_unknown(s->ioaddr); in igb_io_get_reg_index()
166 trace_e1000e_io_read_addr(s->ioaddr); in igb_io_read()
167 return s->ioaddr; in igb_io_read()
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H A De1000e.c72 uint32_t ioaddr; member
118 if (s->ioaddr < 0x1FFFF) { in e1000e_io_get_reg_index()
119 *idx = s->ioaddr; in e1000e_io_get_reg_index()
123 if (s->ioaddr < 0x7FFFF) { in e1000e_io_get_reg_index()
124 trace_e1000e_wrn_io_addr_undefined(s->ioaddr); in e1000e_io_get_reg_index()
128 if (s->ioaddr < 0xFFFFF) { in e1000e_io_get_reg_index()
129 trace_e1000e_wrn_io_addr_flash(s->ioaddr); in e1000e_io_get_reg_index()
133 trace_e1000e_wrn_io_addr_unknown(s->ioaddr); in e1000e_io_get_reg_index()
146 trace_e1000e_io_read_addr(s->ioaddr); in e1000e_io_read()
147 return s->ioaddr; in e1000e_io_read()
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