1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2eee20f81SPatrice Chotard /*
3fb48bc44SPatrice Chotard * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4fb48bc44SPatrice Chotard * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
5eee20f81SPatrice Chotard */
6eee20f81SPatrice Chotard
7eee20f81SPatrice Chotard #include <common.h>
8eee20f81SPatrice Chotard #include <dm.h>
9eee20f81SPatrice Chotard #include <mmc.h>
10dca3166fSPatrice Chotard #include <reset-uclass.h>
11eee20f81SPatrice Chotard #include <sdhci.h>
12eee20f81SPatrice Chotard #include <asm/arch/sdhci.h>
13eee20f81SPatrice Chotard
14eee20f81SPatrice Chotard DECLARE_GLOBAL_DATA_PTR;
15eee20f81SPatrice Chotard
16eee20f81SPatrice Chotard struct sti_sdhci_plat {
17eee20f81SPatrice Chotard struct mmc_config cfg;
18eee20f81SPatrice Chotard struct mmc mmc;
19dca3166fSPatrice Chotard struct reset_ctl reset;
20819c626bSPatrice Chotard int instance;
21eee20f81SPatrice Chotard };
22eee20f81SPatrice Chotard
23eee20f81SPatrice Chotard /**
24eee20f81SPatrice Chotard * sti_mmc_core_config: configure the Arasan HC
25819c626bSPatrice Chotard * @dev : udevice
26819c626bSPatrice Chotard *
27eee20f81SPatrice Chotard * Description: this function is to configure the Arasan MMC HC.
28eee20f81SPatrice Chotard * This should be called when the system starts in case of, on the SoC,
29eee20f81SPatrice Chotard * it is needed to configure the host controller.
30eee20f81SPatrice Chotard * This happens on some SoCs, i.e. StiH410, where the MMC0 inside the flashSS
31eee20f81SPatrice Chotard * needs to be configured as MMC 4.5 to have full capabilities.
32eee20f81SPatrice Chotard * W/o these settings the SDHCI could configure and use the embedded controller
33eee20f81SPatrice Chotard * with limited features.
34eee20f81SPatrice Chotard */
sti_mmc_core_config(struct udevice * dev)35dca3166fSPatrice Chotard static int sti_mmc_core_config(struct udevice *dev)
36eee20f81SPatrice Chotard {
37819c626bSPatrice Chotard struct sti_sdhci_plat *plat = dev_get_platdata(dev);
38819c626bSPatrice Chotard struct sdhci_host *host = dev_get_priv(dev);
39dca3166fSPatrice Chotard int ret;
40eee20f81SPatrice Chotard
41eee20f81SPatrice Chotard /* only MMC1 has a reset line */
42819c626bSPatrice Chotard if (plat->instance) {
43dca3166fSPatrice Chotard ret = reset_deassert(&plat->reset);
44dca3166fSPatrice Chotard if (ret < 0) {
459b643e31SMasahiro Yamada pr_err("MMC1 deassert failed: %d", ret);
46dca3166fSPatrice Chotard return ret;
47dca3166fSPatrice Chotard }
48eee20f81SPatrice Chotard }
49eee20f81SPatrice Chotard
50eee20f81SPatrice Chotard writel(STI_FLASHSS_MMC_CORE_CONFIG_1,
51819c626bSPatrice Chotard host->ioaddr + FLASHSS_MMC_CORE_CONFIG_1);
52eee20f81SPatrice Chotard
53819c626bSPatrice Chotard if (plat->instance) {
54eee20f81SPatrice Chotard writel(STI_FLASHSS_MMC_CORE_CONFIG2,
55819c626bSPatrice Chotard host->ioaddr + FLASHSS_MMC_CORE_CONFIG_2);
56eee20f81SPatrice Chotard writel(STI_FLASHSS_MMC_CORE_CONFIG3,
57819c626bSPatrice Chotard host->ioaddr + FLASHSS_MMC_CORE_CONFIG_3);
58eee20f81SPatrice Chotard } else {
59eee20f81SPatrice Chotard writel(STI_FLASHSS_SDCARD_CORE_CONFIG2,
60819c626bSPatrice Chotard host->ioaddr + FLASHSS_MMC_CORE_CONFIG_2);
61eee20f81SPatrice Chotard writel(STI_FLASHSS_SDCARD_CORE_CONFIG3,
62819c626bSPatrice Chotard host->ioaddr + FLASHSS_MMC_CORE_CONFIG_3);
63eee20f81SPatrice Chotard }
64eee20f81SPatrice Chotard writel(STI_FLASHSS_MMC_CORE_CONFIG4,
65819c626bSPatrice Chotard host->ioaddr + FLASHSS_MMC_CORE_CONFIG_4);
66dca3166fSPatrice Chotard
67dca3166fSPatrice Chotard return 0;
68eee20f81SPatrice Chotard }
69eee20f81SPatrice Chotard
sti_sdhci_probe(struct udevice * dev)70eee20f81SPatrice Chotard static int sti_sdhci_probe(struct udevice *dev)
71eee20f81SPatrice Chotard {
72eee20f81SPatrice Chotard struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
73eee20f81SPatrice Chotard struct sti_sdhci_plat *plat = dev_get_platdata(dev);
74eee20f81SPatrice Chotard struct sdhci_host *host = dev_get_priv(dev);
75819c626bSPatrice Chotard int ret;
76eee20f81SPatrice Chotard
77eee20f81SPatrice Chotard /*
78eee20f81SPatrice Chotard * identify current mmc instance, mmc1 has a reset, not mmc0
79eee20f81SPatrice Chotard * MMC0 is wired to the SD slot,
80eee20f81SPatrice Chotard * MMC1 is wired on the high speed connector
81eee20f81SPatrice Chotard */
82dca3166fSPatrice Chotard ret = reset_get_by_index(dev, 0, &plat->reset);
83dca3166fSPatrice Chotard if (!ret)
84819c626bSPatrice Chotard plat->instance = 1;
85eee20f81SPatrice Chotard else
86dca3166fSPatrice Chotard if (ret == -ENOENT)
87819c626bSPatrice Chotard plat->instance = 0;
88dca3166fSPatrice Chotard else
89dca3166fSPatrice Chotard return ret;
90eee20f81SPatrice Chotard
91dca3166fSPatrice Chotard ret = sti_mmc_core_config(dev);
92dca3166fSPatrice Chotard if (ret)
93dca3166fSPatrice Chotard return ret;
94eee20f81SPatrice Chotard
95eee20f81SPatrice Chotard host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
96eee20f81SPatrice Chotard SDHCI_QUIRK_32BIT_DMA_ADDR |
97eee20f81SPatrice Chotard SDHCI_QUIRK_NO_HISPD_BIT;
98eee20f81SPatrice Chotard
99eee20f81SPatrice Chotard host->host_caps = MMC_MODE_DDR_52MHz;
100eee20f81SPatrice Chotard
101eee20f81SPatrice Chotard ret = sdhci_setup_cfg(&plat->cfg, host, 50000000, 400000);
102eee20f81SPatrice Chotard if (ret)
103eee20f81SPatrice Chotard return ret;
104eee20f81SPatrice Chotard
105eee20f81SPatrice Chotard host->mmc = &plat->mmc;
106eee20f81SPatrice Chotard host->mmc->priv = host;
107eee20f81SPatrice Chotard host->mmc->dev = dev;
108eee20f81SPatrice Chotard upriv->mmc = host->mmc;
109eee20f81SPatrice Chotard
110eee20f81SPatrice Chotard return sdhci_probe(dev);
111eee20f81SPatrice Chotard }
112eee20f81SPatrice Chotard
sti_sdhci_ofdata_to_platdata(struct udevice * dev)113eee20f81SPatrice Chotard static int sti_sdhci_ofdata_to_platdata(struct udevice *dev)
114eee20f81SPatrice Chotard {
115eee20f81SPatrice Chotard struct sdhci_host *host = dev_get_priv(dev);
116eee20f81SPatrice Chotard
117eee20f81SPatrice Chotard host->name = strdup(dev->name);
118a821c4afSSimon Glass host->ioaddr = (void *)devfdt_get_addr(dev);
119eee20f81SPatrice Chotard
120eee20f81SPatrice Chotard host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
121eee20f81SPatrice Chotard "bus-width", 4);
122eee20f81SPatrice Chotard
123eee20f81SPatrice Chotard return 0;
124eee20f81SPatrice Chotard }
125eee20f81SPatrice Chotard
sti_sdhci_bind(struct udevice * dev)126eee20f81SPatrice Chotard static int sti_sdhci_bind(struct udevice *dev)
127eee20f81SPatrice Chotard {
128eee20f81SPatrice Chotard struct sti_sdhci_plat *plat = dev_get_platdata(dev);
129eee20f81SPatrice Chotard
130eee20f81SPatrice Chotard return sdhci_bind(dev, &plat->mmc, &plat->cfg);
131eee20f81SPatrice Chotard }
132eee20f81SPatrice Chotard
133eee20f81SPatrice Chotard static const struct udevice_id sti_sdhci_ids[] = {
134eee20f81SPatrice Chotard { .compatible = "st,sdhci" },
135eee20f81SPatrice Chotard { }
136eee20f81SPatrice Chotard };
137eee20f81SPatrice Chotard
138eee20f81SPatrice Chotard U_BOOT_DRIVER(sti_mmc) = {
139eee20f81SPatrice Chotard .name = "sti_sdhci",
140eee20f81SPatrice Chotard .id = UCLASS_MMC,
141eee20f81SPatrice Chotard .of_match = sti_sdhci_ids,
142eee20f81SPatrice Chotard .bind = sti_sdhci_bind,
143eee20f81SPatrice Chotard .ops = &sdhci_ops,
144eee20f81SPatrice Chotard .ofdata_to_platdata = sti_sdhci_ofdata_to_platdata,
145eee20f81SPatrice Chotard .probe = sti_sdhci_probe,
146eee20f81SPatrice Chotard .priv_auto_alloc_size = sizeof(struct sdhci_host),
147eee20f81SPatrice Chotard .platdata_auto_alloc_size = sizeof(struct sti_sdhci_plat),
148eee20f81SPatrice Chotard };
149