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Searched refs:in_be32 (Results 1 – 25 of 369) sorted by relevance

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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dfsl_lsch2_serdes.c180 reg = in_be32(&serdes1_base->lane[i].gcr0); in setup_serdes_volt()
190 reg = in_be32(&serdes2_base->lane[i].gcr0); in setup_serdes_volt()
231 reg = in_be32(&serdes1_base->srdstcalcr); in setup_serdes_volt()
234 reg = in_be32(&serdes1_base->srdsrcalcr); in setup_serdes_volt()
240 reg = in_be32(&serdes2_base->srdstcalcr); in setup_serdes_volt()
243 reg = in_be32(&serdes2_base->srdsrcalcr); in setup_serdes_volt()
275 reg = in_be32(&serdes1_base->srdstcalcr); in setup_serdes_volt()
278 reg = in_be32(&serdes1_base->srdsrcalcr); in setup_serdes_volt()
301 reg = in_be32(&serdes2_base->srdstcalcr); in setup_serdes_volt()
304 reg = in_be32(&serdes2_base->srdsrcalcr); in setup_serdes_volt()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dimmap.c27 in_be32(&sc->sc_siumcr), in_be32(&sc->sc_sypcr)); in do_siuinfo()
30 in_be32(&sc->sc_sipend), in_be32(&sc->sc_simask)); in do_siuinfo()
32 in_be32(&sc->sc_siel), in_be32(&sc->sc_sivec)); in do_siuinfo()
34 in_be32(&sc->sc_tesr), in_be32(&sc->sc_sdcr)); in do_siuinfo()
49 i, in_be32(p), i, in_be32(p + 1)); in do_memcinfo()
54 in_be32(&memctl->memc_mamr), in_be32(&memctl->memc_mbmr)); in do_memcinfo()
139 binary("PB_DIR", in_be32(R++), PB_NBITS); in do_iopinfo()
141 binary("PB_PAR", in_be32(R++), PB_NBITS); in do_iopinfo()
143 binary("PB_ODR", in_be32(R++), PB_NB_ODR); in do_iopinfo()
145 binary("PB_DAT", in_be32(R++), PB_NBITS); in do_iopinfo()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dmpc8536_serdes.c115 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
122 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
127 tmp = in_be32(sd + FSL_SRDSCR2_OFFS); in fsl_serdes_init()
134 tmp = in_be32(sd + FSL_SRDSCR3_OFFS); in fsl_serdes_init()
143 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
148 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
153 tmp = in_be32(sd + FSL_SRDSCR2_OFFS); in fsl_serdes_init()
158 tmp = in_be32(sd + FSL_SRDSCR3_OFFS); in fsl_serdes_init()
165 tmp = in_be32(sd + FSL_SRDSCR0_OFFS); in fsl_serdes_init()
172 tmp = in_be32(sd + FSL_SRDSCR1_OFFS); in fsl_serdes_init()
[all …]
H A Dfsl_corenet2_serdes.c124 u32 cfg = in_be32(&gur->rcwsr[4]); in serdes_get_first_lane()
211 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; in serdes_init()
224 sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0); in serdes_init()
231 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
266 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); in serdes_init()
275 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
283 pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1); in serdes_init()
293 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2); in serdes_init()
302 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
305 pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2); in serdes_init()
[all …]
H A Dqe_io.c33 in_be32(&par_io[port].cpdir2) : in qe_config_iopin()
34 in_be32(&par_io[port].cpdir1); in qe_config_iopin()
48 tmp_val = in_be32(&par_io[port].cpodr); in qe_config_iopin()
56 in_be32(&par_io[port].cppar2): in qe_config_iopin()
57 in_be32(&par_io[port].cppar1); in qe_config_iopin()
H A Dspeed.c95 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >> in get_sys_info()
113 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> in get_sys_info()
118 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> in get_sys_info()
154 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; in get_sys_info()
189 u32 c_pll_sel = (in_be32 in get_sys_info()
214 rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; in get_sys_info()
216 rcw_tmp = in_be32(&gur->rcwsr[7]); in get_sys_info()
416 rcw_tmp = in_be32(&gur->rcwsr[15]); in get_sys_info()
462 rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]); in get_sys_info()
497 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) in get_sys_info()
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf5445x/
H A Dspeed.c65 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) in clock_exit_limp()
92 temp = in_be32(&pll->pcr); in setup_5441x_clocks()
97 temp = in_be32(&pll->pdr); in setup_5441x_clocks()
106 vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) * in setup_5441x_clocks()
112 pdr = in_be32(&pll->pdr); in setup_5441x_clocks()
173 pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF; in setup_5445x_clocks()
188 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000; in setup_5445x_clocks()
204 j = (in_be32(&pll->pcr) & 0xFF000000) >> 24; in setup_5445x_clocks()
215 pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF; in setup_5445x_clocks()
227 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); in setup_5445x_clocks()
[all …]
/openbmc/u-boot/drivers/ddr/fsl/
H A Dmpc85xx_ddr_gen3.c209 save1 = in_be32(&ddr->debug[12]); in fsl_ddr_set_memctl_regs()
210 save2 = in_be32(&ddr->debug[21]); in fsl_ddr_set_memctl_regs()
217 while (!(in_be32(&ddr->debug[1]) & 0x2)) in fsl_ddr_set_memctl_regs()
231 while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN) in fsl_ddr_set_memctl_regs()
324 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000) in fsl_ddr_set_memctl_regs()
347 && in_be32(&ddr->sdram_cfg) & 0x80000) { in fsl_ddr_set_memctl_regs()
366 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
452 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
461 in_be32(&ddr->timing_cfg_2)); in fsl_ddr_set_memctl_regs()
476 while (in_be32(&ddr->debug[1]) & 0x800) in fsl_ddr_set_memctl_regs()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dserdes.c55 tmp = in_be32(regs + FSL_SRDSCR0_OFFS); in fsl_setup_serdes()
60 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
69 tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); in fsl_setup_serdes()
82 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
87 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
105 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
110 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
127 tmp = in_be32(regs + FSL_SRDSCR1_OFFS); in fsl_setup_serdes()
132 tmp = in_be32(regs + FSL_SRDSCR2_OFFS); in fsl_setup_serdes()
149 tmp = in_be32(regs + FSL_SRDSRSTCTL_OFFS); in fsl_setup_serdes()
H A Dqe_io.c31 in_be32(&par_io->ioport[port].dir2) : in qe_config_iopin()
32 in_be32(&par_io->ioport[port].dir1); in qe_config_iopin()
46 tmp_val = in_be32(&par_io->ioport[port].podr); in qe_config_iopin()
55 in_be32(&par_io->ioport[port].ppar2): in qe_config_iopin()
56 in_be32(&par_io->ioport[port].ppar1); in qe_config_iopin()
/openbmc/linux/drivers/edac/
H A Dmpc85xx_edac.c69 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); in mpc85xx_pci_check()
73 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); in mpc85xx_pci_check()
75 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); in mpc85xx_pci_check()
99 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0)); in mpc85xx_pcie_check()
101 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R1)); in mpc85xx_pcie_check()
103 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R2)); in mpc85xx_pcie_check()
105 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R3)); in mpc85xx_pcie_check()
225 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR); in mpc85xx_pci_err_probe()
228 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); in mpc85xx_pci_err_probe()
238 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); in mpc85xx_pci_err_probe()
[all …]
/openbmc/u-boot/drivers/net/fm/
H A Dtgec_phy.c32 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_write()
43 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_write()
50 while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY) in tgec_mdio_write()
74 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_read()
85 while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY) in tgec_mdio_read()
93 while ((in_be32(&regs->mdio_data)) & MDIO_DATA_BSY) in tgec_mdio_read()
97 if (in_be32(&regs->mdio_stat) & MDIO_STAT_RD_ER) in tgec_mdio_read()
100 return in_be32(&regs->mdio_data) & 0xffff; in tgec_mdio_read()
/openbmc/u-boot/arch/m68k/cpu/mcf5227x/
H A Dspeed.c63 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) in clock_exit_limp()
78 pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF; in get_clocks()
90 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
93 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); in get_clocks()
97 ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * in get_clocks()
103 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
112 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1; in get_clocks()
115 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; in get_clocks()
/openbmc/u-boot/drivers/serial/
H A Dserial_xuartlite.c41 if (in_be32(&regs->status) & SR_TX_FIFO_FULL) in uartlite_serial_putc()
54 if (!(in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA)) in uartlite_serial_getc()
57 return in_be32(&regs->rx_fifo) & 0xff; in uartlite_serial_getc()
66 return in_be32(&regs->status) & SR_RX_FIFO_VALID_DATA; in uartlite_serial_pending()
68 return !(in_be32(&regs->status) & SR_TX_FIFO_EMPTY); in uartlite_serial_pending()
78 in_be32(&regs->control); in uartlite_serial_probe()
124 in_be32(&regs->control); in _debug_uart_init()
131 while (in_be32(&regs->status) & SR_TX_FIFO_FULL) in _debug_uart_putc()
/openbmc/linux/drivers/net/ethernet/freescale/
H A Dfec_mpc52xx.c181 rcntrl = in_be32(&fec->r_cntrl); in mpc52xx_fec_adjust_link()
182 tcntrl = in_be32(&fec->x_cntrl); in mpc52xx_fec_adjust_link()
450 ievent = in_be32(&fec->ievent); in mpc52xx_fec_interrupt()
493 in_be32(&fec->rmon_r_oversize) + in mpc52xx_fec_get_stats()
494 in_be32(&fec->rmon_r_frag) + in mpc52xx_fec_get_stats()
495 in_be32(&fec->rmon_r_jab); in mpc52xx_fec_get_stats()
501 in_be32(&fec->rmon_t_oversize) + in mpc52xx_fec_get_stats()
502 in_be32(&fec->rmon_t_frag) + in mpc52xx_fec_get_stats()
503 in_be32(&fec->rmon_t_jab); in mpc52xx_fec_get_stats()
511 + in_be32(&fec->rmon_r_frag) in mpc52xx_fec_get_stats()
[all …]
H A Ducc_geth.c370 u32 val = in_be32(p_start); in dump_init_enet_entries()
382 (in_be32(p_start) & in dump_init_enet_entries()
643 in_be32(&ugeth->ug_regs->tx64)); in dump_regs()
652 in_be32(&ugeth->ug_regs->rx64)); in dump_regs()
661 in_be32(&ugeth->ug_regs->txok)); in dump_regs()
667 in_be32(&ugeth->ug_regs->tmca)); in dump_regs()
670 in_be32(&ugeth->ug_regs->tbca)); in dump_regs()
961 (u32)qe_muram_addr(in_be32 in dump_regs()
965 qe_muram_addr(in_be32 in dump_regs()
1242 value = in_be32(upsmr_register); in init_rx_parameters()
[all …]
/openbmc/u-boot/board/gdsys/common/
H A Dmiiphybb.c27 in_be32((void *)GPIO0_TCR) | pins->mdio); in io_bb_mdio_active()
37 in_be32((void *)GPIO0_TCR) & ~pins->mdio); in io_bb_mdio_tristate()
48 in_be32((void *)GPIO0_OR) | pins->mdio); in io_bb_set_mdio()
51 in_be32((void *)GPIO0_OR) & ~pins->mdio); in io_bb_set_mdio()
60 *v = ((in_be32((void *)GPIO0_IR) & pins->mdio) != 0); in io_bb_get_mdio()
71 in_be32((void *)GPIO0_OR) | pins->mdc); in io_bb_set_mdc()
74 in_be32((void *)GPIO0_OR) & ~pins->mdc); in io_bb_set_mdc()
/openbmc/u-boot/arch/powerpc/cpu/mpc8xxx/
H A Dlaw.c37 ((u64)in_be32(LAWBARH_ADDR(idx)) << 32) | in get_law_base_addr()
38 in_be32(LAWBARL_ADDR(idx)); in get_law_base_addr()
63 in_be32(LAWAR_ADDR(idx)); in set_law()
74 in_be32(LAWAR_ADDR(idx)); in disable_law()
85 lawar = in_be32(LAWAR_ADDR(i)); in get_law_entry()
164 lawar = in_be32(LAWAR_ADDR(i)); in print_laws()
167 i, in_be32(LAWBARH_ADDR(i)), in print_laws()
168 i, in_be32(LAWBARL_ADDR(i))); in print_laws()
229 u32 lawar = in_be32(LAWAR_ADDR(i)); in disable_non_ddr_laws()
284 u32 lawar = in_be32(LAWAR_ADDR(i)); in init_laws()
[all …]
H A Dsrio.c82 conf_lane = (in_be32((void *)&srds_regs->srdspccr0) in srio_erratum_a004034()
84 init_lane = (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
92 if (in_be32((void *)&srds_regs->bank[0].rstctl) in srio_erratum_a004034()
103 if (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
155 in_be32(&srds_regs->lane[idx].gcr0); in srio_erratum_a004034()
172 in_be32(&srds_regs->lane[idx].gcr0); in srio_erratum_a004034()
192 (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
194 if (in_be32((void *)&srio_regs->lp_serial in srio_erratum_a004034()
213 if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr) in srio_erratum_a004034()
410 while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT in srio_boot_master_release_slave()
[all …]
/openbmc/linux/arch/powerpc/platforms/cell/spufs/
H A Dhw_ops.c32 mbox_stat = in_be32(&prob->mb_stat_R); in spu_hw_mbox_read()
34 *data = in_be32(&prob->pu_mb_R); in spu_hw_mbox_read()
43 return in_be32(&ctx->spu->problem->mb_stat_R); in spu_hw_mbox_stat_read()
53 stat = in_be32(&spu->problem->mb_stat_R); in spu_hw_mbox_stat_poll()
90 if (in_be32(&prob->mb_stat_R) & 0xff0000) { in spu_hw_ibox_read()
110 if (in_be32(&prob->mb_stat_R) & 0x00ff00) { in spu_hw_wbox_write()
178 return in_be32(&ctx->spu->problem->spu_npc_RW); in spu_hw_npc_read()
188 return in_be32(&ctx->spu->problem->spu_status_R); in spu_hw_status_read()
203 return in_be32(&ctx->spu->problem->spu_runcntl_RW); in spu_hw_runcntl_read()
254 if (in_be32(&prob->dma_querytype_RW)) in spu_hw_set_mfc_query()
[all …]
/openbmc/u-boot/board/xes/common/
H A Dfsl_8xxx_pci.c29 u32 devdisr = in_be32(&gur->devdisr); in pci_init_board()
30 uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD; in pci_init_board()
31 uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32; in pci_init_board()
32 uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB; in pci_init_board()
33 uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1; in pci_init_board()
/openbmc/linux/arch/powerpc/platforms/83xx/
H A Dsuspend.c123 u32 reg_cfg1 = in_be32(&pmc_regs->config1); in mpc83xx_change_state()
145 u32 event = in_be32(&pmc_regs->event); in pmc_irq_handler()
168 saved_regs.sicrl = in_be32(&syscr_regs->sicrl); in mpc83xx_suspend_save_regs()
169 saved_regs.sicrh = in_be32(&syscr_regs->sicrh); in mpc83xx_suspend_save_regs()
170 saved_regs.sccr = in_be32(&clock_regs->sccr); in mpc83xx_suspend_save_regs()
186 in_be32(&pmc_regs->config1) | PMCCR1_PME_EN); in mpc83xx_suspend_enter()
207 in_be32(&pmc_regs->config1) | PMCCR1_POWER_OFF); in mpc83xx_suspend_enter()
214 in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF); in mpc83xx_suspend_enter()
229 in_be32(&pmc_regs->config1) & ~PMCCR1_PME_EN); in mpc83xx_suspend_enter()
308 ret = !(in_be32(&rcw_regs->rcwhr) & RCW_PCI_HOST); in mpc83xx_is_pci_agent()
/openbmc/u-boot/arch/m68k/cpu/mcf532x/
H A Dspeed.c67 u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; in get_sys_clock()
68 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); in get_sys_clock()
69 u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1; in get_sys_clock()
153 u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1; in clock_pll()
154 mfd = (in_be32(&pll->pcr) & 0x3F) + 1; in clock_pll()
199 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) in clock_pll()
232 if (in_be32(&sdram->ctrl) & SDRAMC_SDCR_REF) in clock_pll()
/openbmc/u-boot/drivers/spi/
H A Dfsl_espi.c144 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & in spi_claim_bus()
150 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
155 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
158 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
162 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
166 out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) in spi_claim_bus()
195 event = in_be32(&espi->event); in fsl_espi_tx()
224 tmpdin = in_be32(&espi->rx); in fsl_espi_rx()
313 event = in_be32(&espi->event); in spi_xfer()
323 event = in_be32(&espi->event); in spi_xfer()
[all …]
/openbmc/linux/drivers/char/xilinx_hwicap/
H A Dfifo_icap.c108 u32 data = in_be32(drvdata->base_address + XHI_RF_OFFSET); in fifo_icap_fifo_read()
162 u32 status = in_be32(drvdata->base_address + XHI_SR_OFFSET); in fifo_icap_get_status()
173 u32 status = in_be32(drvdata->base_address + XHI_SR_OFFSET); in fifo_icap_busy()
186 return in_be32(drvdata->base_address + XHI_WFV_OFFSET); in fifo_icap_write_fifo_vacancy()
198 return in_be32(drvdata->base_address + XHI_RFO_OFFSET); in fifo_icap_read_fifo_occupancy()
364 reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); in fifo_icap_reset()
385 reg_data = in_be32(drvdata->base_address + XHI_CR_OFFSET); in fifo_icap_flush_fifo()

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