209 		save1 = in_be32(&ddr->debug[12]);  in fsl_ddr_set_memctl_regs()
210 		save2 = in_be32(&ddr->debug[21]);  in fsl_ddr_set_memctl_regs()
217 		while (!(in_be32(&ddr->debug[1]) & 0x2))  in fsl_ddr_set_memctl_regs()
231 			while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)  in fsl_ddr_set_memctl_regs()
251 			while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)  in fsl_ddr_set_memctl_regs()
271 			while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)  in fsl_ddr_set_memctl_regs()
291 			while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)  in fsl_ddr_set_memctl_regs()
311 			while (in_be32(&ddr->sdram_md_cntl) & MD_CNTL_MD_EN)  in fsl_ddr_set_memctl_regs()
324 		while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)  in fsl_ddr_set_memctl_regs()
346 	if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)  in fsl_ddr_set_memctl_regs()
347 	    && in_be32(&ddr->sdram_cfg) & 0x80000) {  in fsl_ddr_set_memctl_regs()
361 	debug("Setting EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));  in fsl_ddr_set_memctl_regs()
366 		in_be32(&ddr->sdram_cfg_2));  in fsl_ddr_set_memctl_regs()
370 	debug("Setting DEBUG_3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));  in fsl_ddr_set_memctl_regs()
389 		temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);  in fsl_ddr_set_memctl_regs()
392 		temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);  in fsl_ddr_set_memctl_regs()
432 	while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&  in fsl_ddr_set_memctl_regs()
446 	debug("Clearing D3[21] to 0x%08x\n", in_be32(&ddr->debug[2]));  in fsl_ddr_set_memctl_regs()
452 		in_be32(&ddr->sdram_cfg_2));  in fsl_ddr_set_memctl_regs()
456 	debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));  in fsl_ddr_set_memctl_regs()
461 		in_be32(&ddr->timing_cfg_2));  in fsl_ddr_set_memctl_regs()
465 	debug("Setting D6 to 0x%08x\n", in_be32(&ddr->debug[5]));  in fsl_ddr_set_memctl_regs()
469 	debug("Setting D7 to 0x%08x\n", in_be32(&ddr->debug[6]));  in fsl_ddr_set_memctl_regs()
473 	debug("Setting D2[20] to 0x%08x\n", in_be32(&ddr->debug[1]));  in fsl_ddr_set_memctl_regs()
476 	while (in_be32(&ddr->debug[1]) & 0x800)  in fsl_ddr_set_memctl_regs()
481 	debug("Setting D1[15] to 0x%08x\n", in_be32(&ddr->debug[0]));  in fsl_ddr_set_memctl_regs()
486 	debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));  in fsl_ddr_set_memctl_regs()
491 	debug("Setting D2[21] to 0x%08x\n", in_be32(&ddr->debug[1]));  in fsl_ddr_set_memctl_regs()
494 	while (in_be32(&ddr->debug[1]) & 0x400)  in fsl_ddr_set_memctl_regs()
504 	debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));  in fsl_ddr_set_memctl_regs()
509 	while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&  in fsl_ddr_set_memctl_regs()
520 	debug("Clearing EEBACR[3] to 0x%08x\n", in_be32(&ecm->eebacr));  in fsl_ddr_set_memctl_regs()