Lines Matching refs:in_be32
83 porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT in get_sys_info()
95 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >> in get_sys_info()
112 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; in get_sys_info()
113 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> in get_sys_info()
118 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> in get_sys_info()
154 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f; in get_sys_info()
178 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27) in get_sys_info()
189 u32 c_pll_sel = (in_be32 in get_sys_info()
214 rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; in get_sys_info()
216 rcw_tmp = in_be32(&gur->rcwsr[7]); in get_sys_info()
267 rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/ in get_sys_info()
268 rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/ in get_sys_info()
416 rcw_tmp = in_be32(&gur->rcwsr[15]); in get_sys_info()
462 rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]); in get_sys_info()
497 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27) in get_sys_info()
517 rcw_tmp = in_be32(&gur->rcwsr[7]); in get_sys_info()