| /openbmc/u-boot/arch/microblaze/cpu/ |
| H A D | interrupts.c | 52 mask = intc->ier; in enable_one_interrupt()
53 intc->ier = (mask | offset); in enable_one_interrupt()
56 intc->ier); in enable_one_interrupt()
57 debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, in enable_one_interrupt()
67 mask = intc->ier; in disable_one_interrupt()
68 intc->ier = (mask & ~offset); in disable_one_interrupt()
71 intc->ier); in disable_one_interrupt()
72 debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, in disable_one_interrupt()
105 intc->ier = 0; in intc_init()
110 debug("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier, in intc_init()
[all …]
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| /openbmc/qemu/hw/gpio/ |
| H A D | mpc8xxx.c | 41 uint32_t ier; member
54 VMSTATE_UINT32(ier, MPC8XXXGPIOState),
63 qemu_set_irq(s->irq, !!(s->ier & s->imr)); in mpc8xxx_gpio_update()
84 return s->ier; in mpc8xxx_gpio_read()
136 s->ier &= ~value; in mpc8xxx_gpio_write()
156 s->ier = 0; in mpc8xxx_gpio_reset()
175 s->ier |= mask; in mpc8xxx_gpio_set_irq()
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| /openbmc/qemu/hw/timer/ |
| H A D | mss-timer.c | 62 bool isr, ier; in timer_update_irq() local
65 ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); in timer_update_irq()
66 qemu_set_irq(st->irq, (ier && isr)); in timer_update_irq()
93 int ier; in timer_read() local
114 ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); in timer_read()
115 ret = ier & isr; in timer_read()
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| /openbmc/qemu/hw/char/ |
| H A D | bcm2835_aux.c | 57 if ((s->ier & RX_INT) && s->read_count != 0) { in bcm2835_aux_update()
60 if (s->ier & TX_INT) { in bcm2835_aux_update()
93 return 0xc0 | s->ier; /* FIFO enables always read 1 */ in bcm2835_aux_read()
182 s->ier = value & (TX_INT | RX_INT); in bcm2835_aux_write()
270 VMSTATE_UINT8(ier, BCM2835AuxState),
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| H A D | serial.c | 122 if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) { in serial_update_irq()
124 } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) { in serial_update_irq()
129 } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) && in serial_update_irq()
133 } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) { in serial_update_irq()
135 } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) { in serial_update_irq()
368 uint8_t changed = (s->ier ^ val) & 0x0f; in serial_ioport_write()
369 s->ier = val & 0x0f; in serial_ioport_write()
374 if (s->ier & UART_IER_MSI) { in serial_ioport_write()
395 if ((s->ier & UART_IER_THRI) && (s->lsr & UART_LSR_THRE)) { in serial_ioport_write()
505 ret = s->ier; in serial_ioport_read()
[all …]
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| /openbmc/u-boot/drivers/serial/ |
| H A D | serial_mtk.c | 21 u32 ier; member
42 #define dlm ier
176 writel(0, &priv->regs->ier); in mtk_serial_probe()
250 writel(0, &priv.regs->ier); in _debug_uart_init()
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| /openbmc/u-boot/arch/m68k/include/asm/coldfire/ |
| H A D | eport.h | 18 u8 ier; /* 0x05 */ member
28 u8 ier; /* 0x03 Interrupt Enable */
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| H A D | ata.h | 54 u8 ier; /* 0x2C */ member
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| /openbmc/qemu/hw/misc/ |
| H A D | mos6522.c | 56 if (s->ifr & s->ier) { in mos6522_update_irq()
232 if ((s->ier & T1_INT) == 0 || (s->acr & T1MODE) != T1MODE_CONT) { in mos6522_timer1_update()
246 if ((s->ier & T2_INT) == 0) { in mos6522_timer2_update()
376 if (s->ifr & s->ier) { in mos6522_read()
381 val = s->ier | 0x80; in mos6522_read()
483 s->ier |= val & 0x7f; in mos6522_write()
486 s->ier &= ~val; in mos6522_write()
544 mos6522_reg_names[14], s->ier); in qmp_x_query_via_foreach()
637 VMSTATE_UINT8(ier, MOS6522State),
657 s->ier = 0; in mos6522_reset_hold()
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| /openbmc/u-boot/arch/microblaze/include/asm/ |
| H A D | microblaze_intc.h | 11 int ier; /* interrupt enable register */ member
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| /openbmc/u-boot/include/ |
| H A D | ns16550.h | 69 UART_REG(ier); /* 1 */
103 #define dlm ier
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| /openbmc/u-boot/drivers/gpio/ |
| H A D | mpc83xx_gpio.c | 157 out_be32(&im->gpio[0].ier, 0xFFFFFFFF); /* Clear all events */ in mpc83xx_gpio_init_f()
166 out_be32(&im->gpio[1].ier, 0xFFFFFFFF); /* Clear all events */ in mpc83xx_gpio_init_f()
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| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | at91_st.h | 16 u32 ier; member
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| H A D | at91_dbu.h | 18 u32 ier; /* Interrupt Enable Register WO */ member
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| H A D | at91_tc.h | 18 u32 ier; /* 0x24 Interrupt Enable Register */ member
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| H A D | at91_mc.h | 36 u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */ member
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| H A D | at91_spi.h | 23 u32 ier; /* 0x14 Interrupt Enable Register */ member
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | uart.h | 10 unsigned int ier; /* Interrupt enable register. */ member
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| /openbmc/qemu/hw/intc/ |
| H A D | rx_icu.c | 83 enable = icu->ier[n_IRQ / 8] & (1 << (n_IRQ & 7)); in rxicu_request()
190 return icu->ier[reg]; in icu_read()
243 icu->ier[reg] = val; in icu_write()
351 VMSTATE_UINT8_ARRAY(ier, RXICUState, NR_IRQS / 8),
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| /openbmc/u-boot/arch/arm/include/asm/arch-aspeed/ |
| H A D | ahbc_aspeed.h | 22 u32 ier; //0x84 member
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| /openbmc/qemu/hw/net/can/ |
| H A D | trace-events | 2 xlnx_can_update_irq(uint32_t isr, uint32_t ier, uint32_t irq) "ISR: 0x%08x IER: 0x%08x IRQ: 0x%08x"
12 xlnx_canfd_update_irq(char *path, uint32_t isr, uint32_t ier, uint32_t irq) "%s: ISR: 0x%08x IER: 0…
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| /openbmc/qemu/include/hw/intc/ |
| H A D | rx_icu.h | 59 uint8_t ier[NR_IRQS / 8]; member
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| /openbmc/u-boot/arch/m68k/include/asm/ |
| H A D | rtc.h | 20 u32 ier; /* 0x18 Interrupt Enable Register */ member
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| /openbmc/u-boot/arch/arm/include/asm/arch-pxa/ |
| H A D | regs-uart.h | 21 uint32_t ier; member
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| /openbmc/qemu/include/hw/net/ |
| H A D | ftgmac100.h | 46 uint32_t ier; member
|