1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2af930827SMasahiro Yamada /* 3af930827SMasahiro Yamada * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de) 4af930827SMasahiro Yamada */ 5af930827SMasahiro Yamada 6af930827SMasahiro Yamada #ifndef AT91_TC_H 7af930827SMasahiro Yamada #define AT91_TC_H 8af930827SMasahiro Yamada 9af930827SMasahiro Yamada typedef struct at91_tcc { 10af930827SMasahiro Yamada u32 ccr; /* 0x00 Channel Control Register */ 11af930827SMasahiro Yamada u32 cmr; /* 0x04 Channel Mode Register */ 12af930827SMasahiro Yamada u32 reserved1[2]; 13af930827SMasahiro Yamada u32 cv; /* 0x10 Counter Value */ 14af930827SMasahiro Yamada u32 ra; /* 0x14 Register A */ 15af930827SMasahiro Yamada u32 rb; /* 0x18 Register B */ 16af930827SMasahiro Yamada u32 rc; /* 0x1C Register C */ 17af930827SMasahiro Yamada u32 sr; /* 0x20 Status Register */ 18af930827SMasahiro Yamada u32 ier; /* 0x24 Interrupt Enable Register */ 19af930827SMasahiro Yamada u32 idr; /* 0x28 Interrupt Disable Register */ 20af930827SMasahiro Yamada u32 imr; /* 0x2C Interrupt Mask Register */ 21af930827SMasahiro Yamada u32 reserved3[4]; 22af930827SMasahiro Yamada } at91_tcc_t; 23af930827SMasahiro Yamada 24af930827SMasahiro Yamada #define AT91_TC_CCR_CLKEN 0x00000001 25af930827SMasahiro Yamada #define AT91_TC_CCR_CLKDIS 0x00000002 26af930827SMasahiro Yamada #define AT91_TC_CCR_SWTRG 0x00000004 27af930827SMasahiro Yamada 28af930827SMasahiro Yamada #define AT91_TC_CMR_CPCTRG 0x00004000 29af930827SMasahiro Yamada 30af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_CLOCK1 0x00000000 31af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_CLOCK2 0x00000001 32af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_CLOCK3 0x00000002 33af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_CLOCK4 0x00000003 34af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_CLOCK5 0x00000004 35af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_XC0 0x00000005 36af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_XC1 0x00000006 37af930827SMasahiro Yamada #define AT91_TC_CMR_TCCLKS_XC2 0x00000007 38af930827SMasahiro Yamada 39af930827SMasahiro Yamada typedef struct at91_tc { 40af930827SMasahiro Yamada at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */ 41af930827SMasahiro Yamada u32 bcr; /* 0xC0 TC Block Control Register */ 42af930827SMasahiro Yamada u32 bmr; /* 0xC4 TC Block Mode Register */ 43af930827SMasahiro Yamada } at91_tc_t; 44af930827SMasahiro Yamada 45af930827SMasahiro Yamada #define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000 46af930827SMasahiro Yamada #define AT91_TC_BMR_TC0XC0S_NONE 0x00000001 47af930827SMasahiro Yamada #define AT91_TC_BMR_TC0XC0S_TIOA1 0x00000002 48af930827SMasahiro Yamada #define AT91_TC_BMR_TC0XC0S_TIOA2 0x00000003 49af930827SMasahiro Yamada 50af930827SMasahiro Yamada #define AT91_TC_BMR_TC1XC1S_TCLK1 0x00000000 51af930827SMasahiro Yamada #define AT91_TC_BMR_TC1XC1S_NONE 0x00000004 52af930827SMasahiro Yamada #define AT91_TC_BMR_TC1XC1S_TIOA0 0x00000008 53af930827SMasahiro Yamada #define AT91_TC_BMR_TC1XC1S_TIOA2 0x0000000C 54af930827SMasahiro Yamada 55af930827SMasahiro Yamada #define AT91_TC_BMR_TC2XC2S_TCLK2 0x00000000 56af930827SMasahiro Yamada #define AT91_TC_BMR_TC2XC2S_NONE 0x00000010 57af930827SMasahiro Yamada #define AT91_TC_BMR_TC2XC2S_TIOA0 0x00000020 58af930827SMasahiro Yamada #define AT91_TC_BMR_TC2XC2S_TIOA1 0x00000030 59af930827SMasahiro Yamada 60af930827SMasahiro Yamada #endif 61