1*979d74d9Sryan_chen #ifndef __AHBC_ASPEED_H_INCLUDED 2*979d74d9Sryan_chen #define __AHBC_ASPEED_H_INCLUDED 3*979d74d9Sryan_chen 4*979d74d9Sryan_chen struct aspeed_ahbc_reg { 5*979d74d9Sryan_chen u32 protection_key; //0x00 6*979d74d9Sryan_chen u32 reserved0[15]; 7*979d74d9Sryan_chen u32 cmd_recod; //0x40 8*979d74d9Sryan_chen u32 log_buff; //0x44 9*979d74d9Sryan_chen u32 polling_addr; //0x48 10*979d74d9Sryan_chen u32 hw_fifo_sts; //0x4C 11*979d74d9Sryan_chen u32 reserved1[3]; 12*979d74d9Sryan_chen u32 hw_fifo_merge; //0x5C 13*979d74d9Sryan_chen u32 hw_fifo_stage0; //0x60 14*979d74d9Sryan_chen u32 hw_fifo_stage1; //0x64 15*979d74d9Sryan_chen u32 hw_fifo_stage2; //0x68 16*979d74d9Sryan_chen u32 hw_fifo_stage3; //0x6C 17*979d74d9Sryan_chen u32 hw_fifo_stage4; //0x70 18*979d74d9Sryan_chen u32 hw_fifo_stage5; //0x74 19*979d74d9Sryan_chen u32 hw_fifo_stage6; //0x78 20*979d74d9Sryan_chen u32 hw_fifo_stage7; //0x7C 21*979d74d9Sryan_chen u32 priority_ctrl; //0x80 22*979d74d9Sryan_chen u32 ier; //0x84 23*979d74d9Sryan_chen u32 target_disable_ctrl; //0x88 24*979d74d9Sryan_chen u32 addr_remap; //0x8C 25*979d74d9Sryan_chen u32 wdt_count_sts; //0x90 26*979d74d9Sryan_chen u32 wdt_count_reload; //0x94 27*979d74d9Sryan_chen }; 28*979d74d9Sryan_chen 29*979d74d9Sryan_chen extern void aspeed_ahbc_remap_enable(struct aspeed_ahbc_reg *ahbc); 30*979d74d9Sryan_chen 31*979d74d9Sryan_chen #endif 32