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Searched refs:gt (Results 1 – 25 of 372) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_pm.c35 intel_gt_pm_get(gt); in user_forcewake()
42 intel_gt_pm_put(gt); in user_forcewake()
60 gt->stats.total = in runtime_end()
69 struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref); in __gt_unpark() local
72 GT_TRACE(gt, "\n"); in __gt_unpark()
94 runtime_begin(gt); in __gt_unpark()
101 struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref); in __gt_park() local
105 GT_TRACE(gt, "\n"); in __gt_park()
107 runtime_end(gt); in __gt_park()
140 intel_wakeref_init(&gt->wakeref, gt->i915, &wf_ops); in intel_gt_pm_init_early()
[all …]
H A Dintel_gt.c113 gt->ggtt = to_gt(gt->i915)->ggtt; in intel_gt_assign_ggtt()
115 gt->ggtt = i915_ggtt_create(gt->i915); in intel_gt_assign_ggtt()
120 list_add_tail(&gt->ggtt_link, &gt->ggtt->gt_list); in intel_gt_assign_ggtt()
451 intel_gsc_init(&gt->gsc, gt->i915); in intel_gt_driver_register()
707 gt->vm = kernel_vm(gt); in intel_gt_init()
745 intel_migrate_init(&gt->migrate, gt); in intel_gt_init()
876 intel_uncore_init_early(gt->uncore, gt); in intel_gt_tile_setup()
909 gt_dbg(gt, "Setting up %s\n", gt->name); in intel_gt_probe_all()
914 i915->gt[0] = gt; in intel_gt_probe_all()
934 gt_dbg(gt, "Setting up %s\n", gt->name); in intel_gt_probe_all()
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H A Dintel_gt_irq.c133 gt = pick_gt(gt, class, instance); in gen11_gt_identity_handler()
228 if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2)) in gen11_gt_irq_reset()
230 if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4)) in gen11_gt_irq_reset()
232 if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6)) in gen11_gt_irq_reset()
234 if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8)) in gen11_gt_irq_reset()
238 if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5)) in gen11_gt_irq_reset()
240 if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7)) in gen11_gt_irq_reset()
245 if (HAS_ENGINE(gt, CCS0) || HAS_ENGINE(gt, CCS1)) in gen11_gt_irq_reset()
348 gt->pm_imr = ~gt->pm_ier; in gen11_gt_irq_postinstall()
478 gt->pm_imr = ~gt->pm_ier; in gen8_gt_irq_postinstall()
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H A Dintel_gt_pm.h16 return intel_wakeref_is_active(&gt->wakeref); in intel_gt_pm_is_awake()
21 intel_wakeref_get(&gt->wakeref); in intel_gt_pm_get()
26 __intel_wakeref_get(&gt->wakeref); in __intel_gt_pm_get()
36 intel_wakeref_might_get(&gt->wakeref); in intel_gt_pm_might_get()
41 intel_wakeref_put(&gt->wakeref); in intel_gt_pm_put()
46 intel_wakeref_put_async(&gt->wakeref); in intel_gt_pm_put_async()
51 intel_wakeref_might_put(&gt->wakeref); in intel_gt_pm_might_put()
54 #define with_intel_gt_pm(gt, tmp) \ argument
55 for (tmp = 1, intel_gt_pm_get(gt); tmp; \
56 intel_gt_pm_put(gt), tmp = 0)
[all …]
H A Dintel_reset.c307 GT_TRACE(gt, in gen6_hw_domain_reset()
649 __gen11_reset_engines(gt, gt->info.engine_mask, 0); in gen8_reset_engines()
738 __reset_guc(gt); in wa_14015076503_start()
897 revoke_mmaps(gt); in gt_revoke()
1186 GT_TRACE(gt, "flags=%lx\n", gt->reset.flags); in intel_gt_reset()
1195 gt_revoke(gt); in intel_gt_reset()
1283 struct intel_gt *gt = engine->gt; in __intel_engine_reset_bh() local
1437 intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) { in intel_gt_handle_error()
1595 i915_gem_shrinker_taints_mutex(gt->i915, &gt->reset.mutex); in intel_gt_init_reset()
1621 w->gt = gt; in __intel_init_wedge()
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H A Dintel_gt_mcr.c146 spin_lock_init(&gt->mcr_lock); in intel_gt_mcr_init()
153 gt->info.mslice_mask = in intel_gt_mcr_init()
156 gt->info.mslice_mask |= in intel_gt_mcr_init()
204 gt->info.l3bank_mask = in intel_gt_mcr_init()
338 intel_gt_mcr_lock(gt, &flags); in rw_with_mcr_steering()
366 __acquires(&gt->mcr_lock) in intel_gt_mcr_lock()
430 __releases(&gt->mcr_lock) in intel_gt_mcr_unlock()
494 intel_gt_mcr_lock(gt, &flags); in intel_gt_mcr_multicast_write()
653 if ((VDBOX_MASK(gt) | VEBOX_MASK(gt) | gt->info.sfc_mask) & BIT(0)) in get_nonterminated_steering()
760 struct intel_gt *gt, in report_steering_type() argument
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H A Dintel_gt.h21 #define IS_GFX_GT_IP_RANGE(gt, from, until) ( \ argument
24 ((gt)->type != GT_MEDIA && \
25 GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
26 GRAPHICS_VER_FULL((gt)->i915) <= (until)))
48 #define GT_TRACE(gt, fmt, ...) do { \ argument
56 return !gt->info.id; in gt_is_root()
61 return MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0) && gt->type == GT_MEDIA; in intel_gt_needs_wa_22016122933()
91 int intel_gt_assign_ggtt(struct intel_gt *gt);
92 int intel_gt_init_mmio(struct intel_gt *gt);
94 int intel_gt_init(struct intel_gt *gt);
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H A Dintel_gt_pm_irq.c17 u32 mask = gt->pm_imr; in write_pm_imr()
40 lockdep_assert_held(gt->irq_lock); in gen6_gt_pm_update_irq()
42 new_val = gt->pm_imr; in gen6_gt_pm_update_irq()
46 if (new_val != gt->pm_imr) { in gen6_gt_pm_update_irq()
47 gt->pm_imr = new_val; in gen6_gt_pm_update_irq()
48 write_pm_imr(gt); in gen6_gt_pm_update_irq()
78 u32 mask = gt->pm_ier; in write_pm_ier()
97 gt->pm_ier |= enable_mask; in gen6_gt_pm_enable_irq()
98 write_pm_ier(gt); in gen6_gt_pm_enable_irq()
106 gt->pm_ier &= ~disable_mask; in gen6_gt_pm_disable_irq()
[all …]
H A Dselftest_reset.c51 igt_global_reset_lock(gt); in __igt_reset_stolen()
249 intel_gt_set_wedged(gt); in igt_wedged_reset()
268 intel_gt_pm_get(gt); in igt_atomic_reset()
272 if (!igt_force_reset(gt)) in igt_atomic_reset()
286 reset_finish(gt, awake); in igt_atomic_reset()
295 igt_force_reset(gt); in igt_atomic_reset()
299 intel_gt_pm_put(gt); in igt_atomic_reset()
320 intel_gt_pm_get(gt); in igt_atomic_engine_reset()
324 if (!igt_force_reset(gt)) in igt_atomic_engine_reset()
364 igt_force_reset(gt); in igt_atomic_engine_reset()
[all …]
H A Dintel_tlb.c62 intel_gt_mcr_lock(gt, &flags); in mmio_invalidate_full()
66 for_each_engine(engine, gt, id) { in mmio_invalidate_full()
71 intel_gt_mcr_multicast_write_fw(gt, in mmio_invalidate_full()
94 intel_gt_mcr_unlock(gt, flags); in mmio_invalidate_full()
98 gt_err_ratelimited(gt, in mmio_invalidate_full()
114 u32 cur = intel_gt_tlb_seqno(gt); in tlb_seqno_passed()
127 if (intel_gt_is_wedged(gt)) in intel_gt_invalidate_tlb_full()
130 if (tlb_seqno_passed(gt, seqno)) in intel_gt_invalidate_tlb_full()
135 if (tlb_seqno_passed(gt, seqno)) in intel_gt_invalidate_tlb_full()
138 mmio_invalidate_full(gt); in intel_gt_invalidate_tlb_full()
[all …]
H A Dintel_gt_sysfs_pm.c31 struct intel_gt *gt; in sysfs_gt_attribute_w_func() local
40 ret = func(gt, val); in sysfs_gt_attribute_w_func()
46 ret = func(gt, val); in sysfs_gt_attribute_w_func()
57 struct intel_gt *gt; in sysfs_gt_attribute_r_func() local
68 u32 val = func(gt); in sysfs_gt_attribute_r_func()
84 ret = func(gt); in sysfs_gt_attribute_r_func()
183 if (HAS_RC6(gt->i915)) in get_rc6_mask()
185 if (HAS_RC6p(gt->i915)) in get_rc6_mask()
320 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) { in intel_sysfs_rc6_init()
496 bool val = rps_read_mask_mmio(&gt->rps, t_attr->reg32(gt), t_attr->mask); in throttle_reason_bool_show()
[all …]
H A Dintel_gt_sysfs.c51 return &gt->i915->drm.primary->kdev->kobj; in gt_get_parent_obj()
60 return sysfs_emit(buf, "%u\n", gt->info.id); in id_show()
91 if (gt_is_root(gt)) in intel_gt_sysfs_register()
92 intel_gt_sysfs_pm_init(gt, gt_get_parent_obj(gt)); in intel_gt_sysfs_register()
96 gt->i915->sysfs_gt, "gt%d", gt->info.id)) in intel_gt_sysfs_register()
99 gt->sysfs_defaults = kobject_create_and_add(".defaults", &gt->sysfs_gt); in intel_gt_sysfs_register()
100 if (!gt->sysfs_defaults) in intel_gt_sysfs_register()
103 intel_gt_sysfs_pm_init(gt, &gt->sysfs_gt); in intel_gt_sysfs_register()
108 kobject_put(&gt->sysfs_gt); in intel_gt_sysfs_register()
114 kobject_put(gt->sysfs_defaults); in intel_gt_sysfs_unregister()
[all …]
H A Dintel_reset.h21 void intel_gt_init_reset(struct intel_gt *gt);
22 void intel_gt_fini_reset(struct intel_gt *gt);
25 void intel_gt_handle_error(struct intel_gt *gt,
31 void intel_gt_reset(struct intel_gt *gt,
45 void intel_gt_set_wedged(struct intel_gt *gt);
46 bool intel_gt_unset_wedged(struct intel_gt *gt);
47 int intel_gt_terminally_wedged(struct intel_gt *gt);
59 int intel_reset_guc(struct intel_gt *gt);
63 struct intel_gt *gt; member
68 struct intel_gt *gt,
[all …]
H A Dintel_gt_clock_utils.c177 gt->clock_frequency = read_clock_frequency(gt->uncore); in intel_gt_init_clock_frequency()
180 if (GRAPHICS_VER(gt->i915) == 11) in intel_gt_init_clock_frequency()
182 else if (gt->clock_frequency) in intel_gt_init_clock_frequency()
183 gt->clock_period_ns = intel_gt_clock_interval_to_ns(gt, 1); in intel_gt_init_clock_frequency()
185 GT_TRACE(gt, in intel_gt_init_clock_frequency()
187 gt->clock_frequency / 1000, in intel_gt_init_clock_frequency()
188 gt->clock_period_ns, in intel_gt_init_clock_frequency()
196 if (gt->clock_frequency != read_clock_frequency(gt->uncore)) { in intel_gt_check_clock_frequency()
198 gt->clock_frequency, in intel_gt_check_clock_frequency()
199 read_clock_frequency(gt->uncore)); in intel_gt_check_clock_frequency()
[all …]
H A Dselftest_slpc.c22 struct intel_gt *gt; member
314 intel_gt_pm_get(gt); in run_test()
400 intel_gt_pm_put(gt); in run_test()
410 struct intel_gt *gt; in live_slpc_vary_min() local
414 for_each_gt(gt, i915, i) { in live_slpc_vary_min()
426 struct intel_gt *gt; in live_slpc_vary_max() local
443 struct intel_gt *gt; in live_slpc_max_granted() local
459 struct intel_gt *gt; in live_slpc_power() local
482 struct intel_gt *gt; in live_slpc_tile_interaction() local
498 threads[i].gt = gt; in live_slpc_tile_interaction()
[all …]
H A Dintel_gt_debugfs.c19 int ret = intel_gt_terminally_wedged(gt); in intel_gt_debugfs_reset_show()
36 wait_event(gt->reset.queue, in intel_gt_debugfs_reset_store()
39 intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE, in intel_gt_debugfs_reset_store()
65 struct intel_gt *gt = m->private; in steering_show() local
67 intel_gt_mcr_report_steering(&p, gt, true); in steering_show()
88 if (!gt->i915->drm.primary->debugfs_root) in intel_gt_debugfs_register()
96 gt_debugfs_register(gt, root); in intel_gt_debugfs_register()
98 intel_gt_engines_debugfs_register(gt, root); in intel_gt_debugfs_register()
99 intel_gt_pm_debugfs_register(gt, root); in intel_gt_debugfs_register()
100 intel_sseu_debugfs_register(gt, root); in intel_gt_debugfs_register()
[all …]
H A Dintel_gt_pm_debugfs.c29 atomic_inc(&gt->user_wakeref); in intel_gt_pm_debugfs_forcewake_user_open()
30 intel_gt_pm_get(gt); in intel_gt_pm_debugfs_forcewake_user_open()
31 if (GRAPHICS_VER(gt->i915) >= 6) in intel_gt_pm_debugfs_forcewake_user_open()
39 intel_gt_pm_put(gt); in intel_gt_pm_debugfs_forcewake_user_release()
40 atomic_dec(&gt->user_wakeref); in intel_gt_pm_debugfs_forcewake_user_release()
276 if (gt->type == GT_MEDIA) { in mtl_drpc()
299 if (gt->type == GT_MEDIA) in mtl_drpc()
461 return HAS_LLC(gt->i915); in llc_eval()
491 str_yes_no(gt->awake), in rps_boost_show()
556 *val = intel_uncore_read(gt->uncore, intel_gt_perf_limit_reasons_reg(gt)); in perf_limit_reasons_get()
[all …]
H A Dselftest_hangcheck.c33 struct intel_gt *gt; member
47 h->gt = gt; in hang_init()
106 struct intel_gt *gt = h->gt; in hang_create_request() local
286 struct intel_gt *gt = arg; in igt_hang_sanitycheck() local
295 err = hang_init(&h, gt); in igt_hang_sanitycheck()
350 struct intel_gt *gt = arg; in igt_reset_nop() local
1315 err = hang_init(&h, gt); in igt_reset_wait()
1450 err = hang_init(&h, gt); in __igt_reset_evict_vma()
1585 return __igt_reset_evict_vma(gt, &gt->ggtt->vm, in igt_reset_evict_ggtt()
1614 return __igt_reset_evict_vma(gt, &gt->ggtt->vm, in igt_reset_evict_fence()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/
H A DMakefile88 gt-y += \
105 gt/intel_gt.o \
119 gt/intel_gtt.o \
120 gt/intel_llc.o \
121 gt/intel_lrc.o \
125 gt/intel_rc6.o \
131 gt/intel_rps.o \
136 gt/intel_tlb.o \
143 gt-$(CONFIG_X86) += gt/intel_ggtt_gmch.o
145 gt-y += \
[all …]
/openbmc/linux/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp_irq.c27 struct intel_gt *gt; in intel_pxp_irq_handler() local
32 gt = pxp->ctrl_gt; in intel_pxp_irq_handler()
34 lockdep_assert_held(gt->irq_lock); in intel_pxp_irq_handler()
64 spin_lock_irq(gt->irq_lock); in pxp_irq_reset()
66 spin_unlock_irq(gt->irq_lock); in pxp_irq_reset()
73 spin_lock_irq(gt->irq_lock); in intel_pxp_irq_enable()
81 spin_unlock_irq(gt->irq_lock); in intel_pxp_irq_enable()
97 spin_lock_irq(gt->irq_lock); in intel_pxp_irq_disable()
100 __pxp_set_interrupts(gt, 0); in intel_pxp_irq_disable()
102 spin_unlock_irq(gt->irq_lock); in intel_pxp_irq_disable()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/selftests/
H A Digt_reset.c14 void igt_global_reset_lock(struct intel_gt *gt) in igt_global_reset_lock() argument
22 wait_event(gt->reset.queue, in igt_global_reset_lock()
25 for_each_engine(engine, gt, id) { in igt_global_reset_lock()
27 &gt->reset.flags)) in igt_global_reset_lock()
33 void igt_global_reset_unlock(struct intel_gt *gt) in igt_global_reset_unlock() argument
38 for_each_engine(engine, gt, id) in igt_global_reset_unlock()
42 wake_up_all(&gt->reset.queue); in igt_global_reset_unlock()
45 bool igt_force_reset(struct intel_gt *gt) in igt_force_reset() argument
47 intel_gt_set_wedged(gt); in igt_force_reset()
48 intel_gt_reset(gt, 0, NULL); in igt_force_reset()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gt/uc/
H A Dselftest_guc_hangcheck.c31 struct intel_gt *gt = arg; in intel_hang_guc() local
47 ctx = kernel_context(gt->i915, NULL); in intel_hang_guc()
53 wakeref = intel_runtime_pm_get(gt->uncore->rpm); in intel_hang_guc()
71 ret = igt_spinner_init(&spin, engine->gt); in intel_hang_guc()
92 ret = intel_reset_guc(gt); in intel_hang_guc()
116 gt_err(gt, "Failed to record a GPU reset\n"); in intel_hang_guc()
142 intel_runtime_pm_put(gt->uncore->rpm, wakeref); in intel_hang_guc()
153 struct intel_gt *gt = to_gt(i915); in intel_guc_hang_check() local
155 if (intel_gt_is_wedged(gt)) in intel_guc_hang_check()
158 if (!intel_uc_uses_guc_submission(&gt->uc)) in intel_guc_hang_check()
[all …]
H A Dintel_gsc_uc.c26 spin_lock_irq(gt->irq_lock); in gsc_work()
29 spin_unlock_irq(gt->irq_lock); in gsc_work()
53 if (intel_uc_uses_huc(&gt->uc) && in gsc_work()
71 drm_err(&gt->i915->drm, in gsc_work()
89 drm_err(&gt->i915->drm, in gsc_work()
110 GEM_BUG_ON(!gt_is_root(gt) && !gt->info.engine_mask); in gsc_engine_supported()
112 if (gt_is_root(gt)) in gsc_engine_supported()
115 mask = gt->info.engine_mask; in gsc_engine_supported()
136 if (!gsc_engine_supported(gt)) { in intel_gsc_uc_init_early()
313 spin_lock_irq(gt->irq_lock); in intel_gsc_uc_load_start()
[all …]
H A Dintel_guc.c87 spin_lock_irq(gt->irq_lock); in gen9_reset_guc_interrupts()
88 gen6_gt_pm_reset_iir(gt, gt->pm_guc_events); in gen9_reset_guc_interrupts()
100 gt->pm_guc_events); in gen9_enable_guc_interrupts()
101 gen6_gt_pm_enable_irq(gt, gt->pm_guc_events); in gen9_enable_guc_interrupts()
116 gen6_gt_pm_disable_irq(gt, gt->pm_guc_events); in gen9_disable_guc_interrupts()
277 IS_DG2(gt->i915)) in guc_ctl_wa_flags()
287 if (IS_DG2(gt->i915)) in guc_ctl_wa_flags()
298 if (IS_DG2_G11(gt->i915)) in guc_ctl_wa_flags()
302 if (!RCS_MASK(gt)) in guc_ctl_wa_flags()
377 gt->clock_frequency, gt->clock_period_ns); in intel_guc_dump_time_info()
[all …]
/openbmc/linux/drivers/media/radio/
H A Dradio-gemtek.c152 struct radio_isa_card *isa = &gt->isa; in gemtek_bu2614_transmit()
155 mute = gt->muted ? GEMTEK_MT : 0x00; in gemtek_bu2614_transmit()
182 struct gemtek *gt = kzalloc(sizeof(*gt), GFP_KERNEL); in gemtek_alloc() local
184 if (gt) in gemtek_alloc()
185 gt->muted = true; in gemtek_alloc()
186 return gt ? &gt->isa : NULL; in gemtek_alloc()
196 if (hardmute && gt->muted) in gemtek_s_frequency()
199 gemtek_bu2614_set(gt, BU2614_PORT, 0); in gemtek_s_frequency()
207 gemtek_bu2614_transmit(gt); in gemtek_s_frequency()
219 gt->muted = mute; in gemtek_s_mute_volume()
[all …]

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