| /openbmc/linux/drivers/regulator/ |
| H A D | mt6380-regulator.c | 92 vosel, vosel_mask, enbit, voselon, _modeset_reg, \ argument
108 .enable_mask = BIT(enbit), \
115 #define MT6380_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ argument
130 .enable_mask = BIT(enbit), \
136 #define MT6380_REG_FIXED(match, vreg, enreg, enbit, volt, \ argument
148 .enable_mask = BIT(enbit), \
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| H A D | mt6331-regulator.c | 88 #define MT6331_LDO_S(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ argument
104 .enable_mask = BIT(enbit), \
112 #define MT6331_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ argument
129 .enable_mask = BIT(enbit), \
136 #define MT6331_REG_FIXED(match, vreg, enreg, enbit, qibit, volt, \ argument
150 .enable_mask = BIT(enbit), \
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| H A D | mt6358-regulator.c | 68 ldo_index_table, enreg, enbit, vosel, \ argument
83 .enable_mask = BIT(enbit), \
117 enreg, enbit, volt) \ argument
128 .enable_mask = BIT(enbit), \
164 ldo_index_table, enreg, enbit, vosel, \ argument
179 .enable_mask = BIT(enbit), \
213 enreg, enbit, volt) \ argument
224 .enable_mask = BIT(enbit), \
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| H A D | mt6397-regulator.c | 65 #define MT6397_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ argument
80 .enable_mask = BIT(enbit), \
85 #define MT6397_REG_FIXED(match, vreg, enreg, enbit, volt) \ argument
96 .enable_mask = BIT(enbit), \
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| H A D | mt6323-regulator.c | 63 #define MT6323_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ argument
78 .enable_mask = BIT(enbit), \
85 #define MT6323_REG_FIXED(match, vreg, enreg, enbit, volt, \ argument
97 .enable_mask = BIT(enbit), \
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| H A D | mt6332-regulator.c | 116 #define MT6332_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ argument
131 .enable_mask = BIT(enbit), \
139 #define MT6332_REG_FIXED(match, vreg, enreg, enbit, qibit, volt, stbit) \ argument
150 .enable_mask = BIT(enbit), \
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| /openbmc/qemu/hw/intc/ |
| H A D | arm_gicv3_cpuif.c | 663 int enbit; in icv_igrpen_read() local
666 enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; in icv_igrpen_read()
667 value = extract64(cs->ich_vmcr_el2, enbit, 1); in icv_igrpen_read()
678 int enbit; in icv_igrpen_write() local
683 enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; in icv_igrpen_write()
685 cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, enbit, 1, value); in icv_igrpen_write()
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