1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright (c) 2017 MediaTek Inc.
4 // Author: Chenglin Xu <chenglin.xu@mediatek.com>
5 
6 #include <linux/module.h>
7 #include <linux/of.h>
8 #include <linux/platform_device.h>
9 #include <linux/regmap.h>
10 #include <linux/regulator/driver.h>
11 #include <linux/regulator/machine.h>
12 #include <linux/regulator/mt6380-regulator.h>
13 #include <linux/regulator/of_regulator.h>
14 
15 /* PMIC Registers */
16 #define MT6380_ALDO_CON_0                         0x0000
17 #define MT6380_BTLDO_CON_0                        0x0004
18 #define MT6380_COMP_CON_0                         0x0008
19 #define MT6380_CPUBUCK_CON_0                      0x000C
20 #define MT6380_CPUBUCK_CON_1                      0x0010
21 #define MT6380_CPUBUCK_CON_2                      0x0014
22 #define MT6380_DDRLDO_CON_0                       0x0018
23 #define MT6380_MLDO_CON_0                         0x001C
24 #define MT6380_PALDO_CON_0                        0x0020
25 #define MT6380_PHYLDO_CON_0                       0x0024
26 #define MT6380_SIDO_CON_0                         0x0028
27 #define MT6380_SIDO_CON_1                         0x002C
28 #define MT6380_SIDO_CON_2                         0x0030
29 #define MT6380_SLDO_CON_0                         0x0034
30 #define MT6380_TLDO_CON_0                         0x0038
31 #define MT6380_STARTUP_CON_0                      0x003C
32 #define MT6380_STARTUP_CON_1                      0x0040
33 #define MT6380_SMPS_TOP_CON_0                     0x0044
34 #define MT6380_SMPS_TOP_CON_1                     0x0048
35 #define MT6380_ANA_CTRL_0                         0x0050
36 #define MT6380_ANA_CTRL_1                         0x0054
37 #define MT6380_ANA_CTRL_2                         0x0058
38 #define MT6380_ANA_CTRL_3                         0x005C
39 #define MT6380_ANA_CTRL_4                         0x0060
40 #define MT6380_SPK_CON9                           0x0064
41 #define MT6380_SPK_CON11                          0x0068
42 #define MT6380_SPK_CON12                          0x006A
43 #define MT6380_CLK_CTRL                           0x0070
44 #define MT6380_PINMUX_CTRL                        0x0074
45 #define MT6380_IO_CTRL                            0x0078
46 #define MT6380_SLP_MODE_CTRL_0                    0x007C
47 #define MT6380_SLP_MODE_CTRL_1                    0x0080
48 #define MT6380_SLP_MODE_CTRL_2                    0x0084
49 #define MT6380_SLP_MODE_CTRL_3                    0x0088
50 #define MT6380_SLP_MODE_CTRL_4                    0x008C
51 #define MT6380_SLP_MODE_CTRL_5                    0x0090
52 #define MT6380_SLP_MODE_CTRL_6                    0x0094
53 #define MT6380_SLP_MODE_CTRL_7                    0x0098
54 #define MT6380_SLP_MODE_CTRL_8                    0x009C
55 #define MT6380_FCAL_CTRL_0                        0x00A0
56 #define MT6380_FCAL_CTRL_1                        0x00A4
57 #define MT6380_LDO_CTRL_0                         0x00A8
58 #define MT6380_LDO_CTRL_1                         0x00AC
59 #define MT6380_LDO_CTRL_2                         0x00B0
60 #define MT6380_LDO_CTRL_3                         0x00B4
61 #define MT6380_LDO_CTRL_4                         0x00B8
62 #define MT6380_DEBUG_CTRL_0                       0x00BC
63 #define MT6380_EFU_CTRL_0                         0x0200
64 #define MT6380_EFU_CTRL_1                         0x0201
65 #define MT6380_EFU_CTRL_2                         0x0202
66 #define MT6380_EFU_CTRL_3                         0x0203
67 #define MT6380_EFU_CTRL_4                         0x0204
68 #define MT6380_EFU_CTRL_5                         0x0205
69 #define MT6380_EFU_CTRL_6                         0x0206
70 #define MT6380_EFU_CTRL_7                         0x0207
71 #define MT6380_EFU_CTRL_8                         0x0208
72 
73 #define MT6380_REGULATOR_MODE_AUTO	0
74 #define MT6380_REGULATOR_MODE_FORCE_PWM	1
75 
76 /*
77  * mt6380 regulators' information
78  *
79  * @desc: standard fields of regulator description
80  * @vselon_reg: Register sections for hardware control mode of bucks
81  * @modeset_reg: Register for controlling the buck/LDO control mode
82  * @modeset_mask: Mask for controlling the buck/LDO control mode
83  */
84 struct mt6380_regulator_info {
85 	struct regulator_desc desc;
86 	u32 vselon_reg;
87 	u32 modeset_reg;
88 	u32 modeset_mask;
89 };
90 
91 #define MT6380_BUCK(match, vreg, min, max, step, volt_ranges, enreg,	\
92 		    vosel, vosel_mask, enbit, voselon, _modeset_reg,	\
93 		    _modeset_mask)					\
94 [MT6380_ID_##vreg] = {							\
95 	.desc = {							\
96 		.name = #vreg,						\
97 		.of_match = of_match_ptr(match),			\
98 		.ops = &mt6380_volt_range_ops,				\
99 		.type = REGULATOR_VOLTAGE,				\
100 		.id = MT6380_ID_##vreg,					\
101 		.owner = THIS_MODULE,					\
102 		.n_voltages = ((max) - (min)) / (step) + 1,		\
103 		.linear_ranges = volt_ranges,				\
104 		.n_linear_ranges = ARRAY_SIZE(volt_ranges),		\
105 		.vsel_reg = vosel,					\
106 		.vsel_mask = vosel_mask,				\
107 		.enable_reg = enreg,					\
108 		.enable_mask = BIT(enbit),				\
109 	},								\
110 	.vselon_reg = voselon,						\
111 	.modeset_reg = _modeset_reg,					\
112 	.modeset_mask = _modeset_mask,					\
113 }
114 
115 #define MT6380_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel,	\
116 		   vosel_mask, _modeset_reg, _modeset_mask)		\
117 [MT6380_ID_##vreg] = {							\
118 	.desc = {							\
119 		.name = #vreg,						\
120 		.of_match = of_match_ptr(match),			\
121 		.ops = &mt6380_volt_table_ops,				\
122 		.type = REGULATOR_VOLTAGE,				\
123 		.id = MT6380_ID_##vreg,					\
124 		.owner = THIS_MODULE,					\
125 		.n_voltages = ARRAY_SIZE(ldo_volt_table),		\
126 		.volt_table = ldo_volt_table,				\
127 		.vsel_reg = vosel,					\
128 		.vsel_mask = vosel_mask,				\
129 		.enable_reg = enreg,					\
130 		.enable_mask = BIT(enbit),				\
131 	},								\
132 	.modeset_reg = _modeset_reg,					\
133 	.modeset_mask = _modeset_mask,					\
134 }
135 
136 #define MT6380_REG_FIXED(match, vreg, enreg, enbit, volt,		\
137 			 _modeset_reg, _modeset_mask)			\
138 [MT6380_ID_##vreg] = {							\
139 	.desc = {							\
140 		.name = #vreg,						\
141 		.of_match = of_match_ptr(match),			\
142 		.ops = &mt6380_volt_fixed_ops,				\
143 		.type = REGULATOR_VOLTAGE,				\
144 		.id = MT6380_ID_##vreg,					\
145 		.owner = THIS_MODULE,					\
146 		.n_voltages = 1,					\
147 		.enable_reg = enreg,					\
148 		.enable_mask = BIT(enbit),				\
149 		.min_uV = volt,						\
150 	},								\
151 	.modeset_reg = _modeset_reg,					\
152 	.modeset_mask = _modeset_mask,					\
153 }
154 
155 static const struct linear_range buck_volt_range1[] = {
156 	REGULATOR_LINEAR_RANGE(600000, 0, 0xfe, 6250),
157 };
158 
159 static const struct linear_range buck_volt_range2[] = {
160 	REGULATOR_LINEAR_RANGE(600000, 0, 0xfe, 6250),
161 };
162 
163 static const struct linear_range buck_volt_range3[] = {
164 	REGULATOR_LINEAR_RANGE(1200000, 0, 0x3c, 25000),
165 };
166 
167 static const unsigned int ldo_volt_table1[] = {
168 	1400000, 1350000, 1300000, 1250000, 1200000, 1150000, 1100000, 1050000,
169 };
170 
171 static const unsigned int ldo_volt_table2[] = {
172 	2200000, 3300000,
173 };
174 
175 static const unsigned int ldo_volt_table3[] = {
176 	1240000, 1390000, 1540000, 1840000,
177 };
178 
179 static const unsigned int ldo_volt_table4[] = {
180 	2200000, 3300000,
181 };
182 
mt6380_regulator_set_mode(struct regulator_dev * rdev,unsigned int mode)183 static int mt6380_regulator_set_mode(struct regulator_dev *rdev,
184 				     unsigned int mode)
185 {
186 	int val = 0;
187 	struct mt6380_regulator_info *info = rdev_get_drvdata(rdev);
188 
189 	switch (mode) {
190 	case REGULATOR_MODE_NORMAL:
191 		val = MT6380_REGULATOR_MODE_AUTO;
192 		break;
193 	case REGULATOR_MODE_FAST:
194 		val = MT6380_REGULATOR_MODE_FORCE_PWM;
195 		break;
196 	default:
197 		return -EINVAL;
198 	}
199 
200 	val <<= ffs(info->modeset_mask) - 1;
201 
202 	return regmap_update_bits(rdev->regmap, info->modeset_reg,
203 				 info->modeset_mask, val);
204 }
205 
mt6380_regulator_get_mode(struct regulator_dev * rdev)206 static unsigned int mt6380_regulator_get_mode(struct regulator_dev *rdev)
207 {
208 	unsigned int val;
209 	unsigned int mode;
210 	int ret;
211 	struct mt6380_regulator_info *info = rdev_get_drvdata(rdev);
212 
213 	ret = regmap_read(rdev->regmap, info->modeset_reg, &val);
214 	if (ret < 0)
215 		return ret;
216 
217 	val &= info->modeset_mask;
218 	val >>= ffs(info->modeset_mask) - 1;
219 
220 	switch (val) {
221 	case MT6380_REGULATOR_MODE_AUTO:
222 		mode = REGULATOR_MODE_NORMAL;
223 		break;
224 	case MT6380_REGULATOR_MODE_FORCE_PWM:
225 		mode = REGULATOR_MODE_FAST;
226 		break;
227 	default:
228 		return -EINVAL;
229 	}
230 
231 	return mode;
232 }
233 
234 static const struct regulator_ops mt6380_volt_range_ops = {
235 	.list_voltage = regulator_list_voltage_linear_range,
236 	.map_voltage = regulator_map_voltage_linear_range,
237 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
238 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
239 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
240 	.enable = regulator_enable_regmap,
241 	.disable = regulator_disable_regmap,
242 	.is_enabled = regulator_is_enabled_regmap,
243 	.set_mode = mt6380_regulator_set_mode,
244 	.get_mode = mt6380_regulator_get_mode,
245 };
246 
247 static const struct regulator_ops mt6380_volt_table_ops = {
248 	.list_voltage = regulator_list_voltage_table,
249 	.map_voltage = regulator_map_voltage_iterate,
250 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
251 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
252 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
253 	.enable = regulator_enable_regmap,
254 	.disable = regulator_disable_regmap,
255 	.is_enabled = regulator_is_enabled_regmap,
256 	.set_mode = mt6380_regulator_set_mode,
257 	.get_mode = mt6380_regulator_get_mode,
258 };
259 
260 static const struct regulator_ops mt6380_volt_fixed_ops = {
261 	.list_voltage = regulator_list_voltage_linear,
262 	.enable = regulator_enable_regmap,
263 	.disable = regulator_disable_regmap,
264 	.is_enabled = regulator_is_enabled_regmap,
265 	.set_mode = mt6380_regulator_set_mode,
266 	.get_mode = mt6380_regulator_get_mode,
267 };
268 
269 /* The array is indexed by id(MT6380_ID_XXX) */
270 static struct mt6380_regulator_info mt6380_regulators[] = {
271 	MT6380_BUCK("buck-vcore1", VCPU, 600000, 1393750, 6250,
272 		    buck_volt_range1, MT6380_ANA_CTRL_3, MT6380_ANA_CTRL_1,
273 		    0xfe, 3, MT6380_ANA_CTRL_1,
274 		    MT6380_CPUBUCK_CON_0, 0x8000000),
275 	MT6380_BUCK("buck-vcore", VCORE, 600000, 1393750, 6250,
276 		    buck_volt_range2, MT6380_ANA_CTRL_3, MT6380_ANA_CTRL_2,
277 		    0xfe, 2, MT6380_ANA_CTRL_2, MT6380_SIDO_CON_0, 0x1000000),
278 	MT6380_BUCK("buck-vrf", VRF, 1200000, 1575000, 25000,
279 		    buck_volt_range3, MT6380_ANA_CTRL_3, MT6380_SIDO_CON_0,
280 		    0x78, 1, MT6380_SIDO_CON_0, MT6380_SIDO_CON_0, 0x8000),
281 	MT6380_LDO("ldo-vm", VMLDO, ldo_volt_table1, MT6380_LDO_CTRL_0,
282 		   1, MT6380_MLDO_CON_0, 0xE000, MT6380_ANA_CTRL_1, 0x4000000),
283 	MT6380_LDO("ldo-va", VALDO, ldo_volt_table2, MT6380_LDO_CTRL_0,
284 		   2, MT6380_ALDO_CON_0, 0x400, MT6380_ALDO_CON_0, 0x20),
285 	MT6380_REG_FIXED("ldo-vphy", VPHYLDO, MT6380_LDO_CTRL_0, 7, 1800000,
286 			 MT6380_PHYLDO_CON_0, 0x80),
287 	MT6380_LDO("ldo-vddr", VDDRLDO, ldo_volt_table3, MT6380_LDO_CTRL_0,
288 		   8, MT6380_DDRLDO_CON_0, 0x3000, MT6380_DDRLDO_CON_0, 0x80),
289 	MT6380_LDO("ldo-vt", VTLDO, ldo_volt_table4, MT6380_LDO_CTRL_0, 3,
290 		   MT6380_TLDO_CON_0, 0x400, MT6380_TLDO_CON_0, 0x20),
291 };
292 
mt6380_regulator_probe(struct platform_device * pdev)293 static int mt6380_regulator_probe(struct platform_device *pdev)
294 {
295 	struct regmap *regmap = dev_get_regmap(pdev->dev.parent, NULL);
296 	struct regulator_config config = {};
297 	struct regulator_dev *rdev;
298 	int i;
299 
300 	for (i = 0; i < MT6380_MAX_REGULATOR; i++) {
301 		config.dev = &pdev->dev;
302 		config.driver_data = &mt6380_regulators[i];
303 		config.regmap = regmap;
304 		rdev = devm_regulator_register(&pdev->dev,
305 					       &mt6380_regulators[i].desc,
306 				&config);
307 		if (IS_ERR(rdev)) {
308 			dev_err(&pdev->dev, "failed to register %s\n",
309 				mt6380_regulators[i].desc.name);
310 			return PTR_ERR(rdev);
311 		}
312 	}
313 	return 0;
314 }
315 
316 static const struct platform_device_id mt6380_platform_ids[] = {
317 	{"mt6380-regulator", 0},
318 	{ /* sentinel */ },
319 };
320 MODULE_DEVICE_TABLE(platform, mt6380_platform_ids);
321 
322 static const struct of_device_id  __maybe_unused mt6380_of_match[] = {
323 	{ .compatible = "mediatek,mt6380-regulator", },
324 	{ /* sentinel */ },
325 };
326 MODULE_DEVICE_TABLE(of, mt6380_of_match);
327 
328 static struct platform_driver mt6380_regulator_driver = {
329 	.driver = {
330 		.name = "mt6380-regulator",
331 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
332 		.of_match_table = of_match_ptr(mt6380_of_match),
333 	},
334 	.probe = mt6380_regulator_probe,
335 	.id_table = mt6380_platform_ids,
336 };
337 
338 module_platform_driver(mt6380_regulator_driver);
339 
340 MODULE_AUTHOR("Chenglin Xu <chenglin.xu@mediatek.com>");
341 MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6380 PMIC");
342 MODULE_LICENSE("GPL v2");
343