| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr.c | 45 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; in rv1_determine_dppclk_threshold()
53 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
59 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
63 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
72 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
78 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
185 clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz; in ramp_up_dispclk_with_dpp()
227 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz in rv1_update_clocks()
275 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) in rv1_update_clocks()
276 || new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz) { in rv1_update_clocks()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 142 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; in dcn20_update_clocks_update_dentist()
237 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn2_update_clocks()
304 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn2_update_clocks()
305 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn2_update_clocks()
314 …ks->disp_dpp_voltage_level_khz = new_clocks->dispclk_khz > new_clocks->dppclk_khz ? new_clocks->di… in dcn2_update_clocks()
339 clk_mgr_base->clks.dispclk_khz / 1000 / 7); in dcn2_update_clocks()
382 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) { in dcn2_update_clocks_fpga()
383 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn2_update_clocks_fpga()
441 clk_mgr_base->clks.dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn2_read_clocks_from_hw_dentist()
458 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz; in dcn2_get_clock()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_clk_mgr.c | 227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
654 pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz; in dce11_pplib_apply_display_requirements()
678 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
694 clk_mgr->clks.dispclk_khz = patched_disp_clk; in dce_update_clocks()
705 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
721 clk_mgr->clks.dispclk_khz = patched_disp_clk; in dce11_update_clocks()
732 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce112_update_clocks()
748 clk_mgr->clks.dispclk_khz = patched_disp_clk; in dce112_update_clocks()
760 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce12_update_clocks()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 103 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn201_update_clocks()
147 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn201_update_clocks()
148 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn201_update_clocks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/ |
| H A D | dce120_clk_mgr.c | 91 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce12_update_clocks()
97 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce12_update_clocks()
107 clk_mgr_base->clks.dispclk_khz = dce112_set_clock(clk_mgr_base, patched_disp_clk); in dce12_update_clocks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/ |
| H A D | dce60_clk_mgr.c | 126 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce60_update_clocks()
140 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce60_update_clocks()
142 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce60_update_clocks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 213 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn3_update_clocks()
294 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn3_update_clocks()
295 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn3_update_clocks()
296 …_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz)); in dcn3_update_clocks()
319 clk_mgr_base->clks.dispclk_khz / 1000 / 7); in dcn3_update_clocks()
438 if (a->dispclk_khz != b->dispclk_khz) in dcn3_are_clock_states_equal()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 194 if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) { in rn_update_clocks()
196 new_clocks->dispclk_khz = clk_mgr_base->clks.dispclk_khz; in rn_update_clocks()
206 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in rn_update_clocks()
207 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in rn_update_clocks()
208 …_base->clks.actual_dispclk_khz = rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); in rn_update_clocks()
249 clk_mgr_base->clks.dispclk_khz / 1000 / 7); in rn_update_clocks()
530 if (a->dispclk_khz != b->dispclk_khz) in rn_are_clock_states_equal()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| H A D | dce110_clk_mgr.c | 231 pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; in dce11_pplib_apply_display_requirements()
255 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
269 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce11_update_clocks()
270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
271 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce11_update_clocks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.c | 197 if (new_clocks->dispclk_khz < MIN_DPP_DISP_CLK) in dcn315_update_clocks()
198 new_clocks->dispclk_khz = MIN_DPP_DISP_CLK; in dcn315_update_clocks()
207 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn315_update_clocks()
209 if (clk_mgr_base->clks.dispclk_khz) in dcn315_update_clocks()
212 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn315_update_clocks()
213 dcn315_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); in dcn315_update_clocks()
214 if (clk_mgr_base->clks.dispclk_khz) in dcn315_update_clocks()
240 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; in dcn315_update_clocks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 204 if (new_clocks->dispclk_khz < 100000) in dcn316_update_clocks()
205 new_clocks->dispclk_khz = 100000; in dcn316_update_clocks()
214 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn316_update_clocks()
217 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn316_update_clocks()
218 dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); in dcn316_update_clocks()
244 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; in dcn316_update_clocks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 286 if (new_clocks->dispclk_khz > 0) { in dcn32_update_dppclk_dispclk_freq()
288 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz; in dcn32_update_dppclk_dispclk_freq()
289 …new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz… in dcn32_update_dppclk_dispclk_freq()
338 if (clk_mgr->base.clks.dispclk_khz == 0) in dcn32_update_clocks_update_dentist()
342 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; in dcn32_update_clocks_update_dentist()
422 …_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr->base.clks.dispclk_khz)); in dcn32_update_clocks_update_dentist()
472 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn32_update_clocks()
616 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn32_update_clocks()
617 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn32_update_clocks()
657 clk_mgr_base->clks.dispclk_khz / 1000 / 7); in dcn32_update_clocks()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| H A D | dce_clk_mgr.c | 208 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
218 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
403 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
417 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce_update_clocks()
419 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce_update_clocks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/ |
| H A D | dce112_clk_mgr.c | 197 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce112_update_clocks()
211 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce112_update_clocks()
213 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce112_update_clocks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.c | 223 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn31_update_clocks()
226 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn31_update_clocks()
227 dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); in dcn31_update_clocks()
253 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; in dcn31_update_clocks()
312 if (a->dispclk_khz != b->dispclk_khz) in dcn31_are_clock_states_equal()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 251 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn314_update_clocks()
254 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn314_update_clocks()
255 dcn314_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); in dcn314_update_clocks()
281 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; in dcn314_update_clocks()
327 if (a->dispclk_khz != b->dispclk_khz) in dcn314_are_clock_states_equal()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 164 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in vg_update_clocks()
165 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in vg_update_clocks()
166 dcn301_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); in vg_update_clocks()
468 if (a->dispclk_khz != b->dispclk_khz) in vg_are_clock_states_equal()
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| /openbmc/linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_trace.h | 494 __field(int, dispclk_khz)
513 __entry->dispclk_khz = clk->dispclk_khz;
537 __entry->dispclk_khz,
571 __field(int, dispclk_khz)
583 __entry->dispclk_khz = clk->dispclk_khz;
597 __entry->dispclk_khz,
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_debug.c | 351 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
359 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 1165 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000); in dcn_validate_bandwidth()
1167 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000); in dcn_validate_bandwidth()
1169 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < in dcn_validate_bandwidth()
1171 context->bw_ctx.bw.dcn.clk.dispclk_khz = in dcn_validate_bandwidth()
1175 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz / in dcn_validate_bandwidth()
1414 dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz); in dcn_find_dcfclk_suits_all()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hw_sequencer.c | 466 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_log_hw_state()
1493 if (dc->clk_mgr->clks.dispclk_khz != 0 && dc->clk_mgr->clks.dppclk_khz != 0) { in dcn10_init_hw()
1494 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz = dc->clk_mgr->clks.dispclk_khz; in dcn10_init_hw()
2735 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < in dcn10_update_dchubp_dpp()
2736 dc->clk_mgr->clks.dispclk_khz) in dcn10_update_dchubp_dpp()
2741 dc->clk_mgr->clks.dispclk_khz / 2; in dcn10_update_dchubp_dpp()
2755 dc->clk_mgr->clks.dispclk_khz / 2 : in dcn10_update_dchubp_dpp()
2756 dc->clk_mgr->clks.dispclk_khz; in dcn10_update_dchubp_dpp()
3855 current_clocks->dispclk_khz = clk_khz; in dcn10_set_clock()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 452 int dispclk_khz; member
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce100/ |
| H A D | dce100_resource.c | 854 context->bw_ctx.bw.dce.dispclk_khz = 681000; in dce100_validate_bandwidth()
857 context->bw_ctx.bw.dce.dispclk_khz = 0; in dce100_validate_bandwidth()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| H A D | dce60_resource.c | 881 context->bw_ctx.bw.dce.dispclk_khz = 681000; in dce60_validate_bandwidth()
884 context->bw_ctx.bw.dce.dispclk_khz = 0; in dce60_validate_bandwidth()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce80/ |
| H A D | dce80_resource.c | 888 context->bw_ctx.bw.dce.dispclk_khz = 681000; in dce80_validate_bandwidth()
891 context->bw_ctx.bw.dce.dispclk_khz = 0; in dce80_validate_bandwidth()
|