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Searched refs:devadr (Results 1 – 13 of 13) sorted by relevance

/openbmc/u-boot/board/cloudengines/pogo_e02/
H A Dpogo_e02.c76 u16 devadr; in reset_phy() local
83 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { in reset_phy()
92 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); in reset_phy()
93 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in reset_phy()
95 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); in reset_phy()
96 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); in reset_phy()
99 miiphy_reset(name, devadr); in reset_phy()
/openbmc/u-boot/board/Seagate/nas220/
H A Dnas220.c91 u16 devadr; in reset_phy() local
98 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { in reset_phy()
107 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); in reset_phy()
108 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in reset_phy()
110 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); in reset_phy()
111 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); in reset_phy()
114 miiphy_reset(name, devadr); in reset_phy()
/openbmc/u-boot/board/Marvell/dreamplug/
H A Ddreamplug.c101 u16 devadr; in mv_phy_88e1116_init() local
107 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { in mv_phy_88e1116_init()
117 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); in mv_phy_88e1116_init()
118 miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg); in mv_phy_88e1116_init()
120 miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg); in mv_phy_88e1116_init()
121 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); in mv_phy_88e1116_init()
124 miiphy_reset(name, devadr); in mv_phy_88e1116_init()
/openbmc/u-boot/board/Marvell/guruplug/
H A Dguruplug.c104 u16 devadr; in mv_phy_88e1121_init() local
110 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { in mv_phy_88e1121_init()
120 miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2); in mv_phy_88e1121_init()
121 miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, &reg); in mv_phy_88e1121_init()
123 miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg); in mv_phy_88e1121_init()
124 miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0); in mv_phy_88e1121_init()
127 miiphy_reset(name, devadr); in mv_phy_88e1121_init()
/openbmc/u-boot/board/Marvell/sheevaplug/
H A Dsheevaplug.c105 u16 devadr; in reset_phy() local
112 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { in reset_phy()
122 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); in reset_phy()
123 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in reset_phy()
125 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); in reset_phy()
126 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); in reset_phy()
129 miiphy_reset(name, devadr); in reset_phy()
/openbmc/u-boot/board/d-link/dns325/
H A Ddns325.c104 u16 devadr; in reset_phy() local
111 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { in reset_phy()
120 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); in reset_phy()
121 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in reset_phy()
123 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); in reset_phy()
124 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); in reset_phy()
127 miiphy_reset(name, devadr); in reset_phy()
/openbmc/u-boot/board/Marvell/openrd/
H A Dopenrd.c116 u16 devadr; in mv_phy_init() local
122 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { in mv_phy_init()
131 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); in mv_phy_init()
132 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in mv_phy_init()
134 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); in mv_phy_init()
135 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); in mv_phy_init()
138 miiphy_reset(name, devadr); in mv_phy_init()
/openbmc/u-boot/board/Seagate/goflexhome/
H A Dgoflexhome.c111 u16 devadr; in reset_phy() local
118 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { in reset_phy()
128 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); in reset_phy()
129 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in reset_phy()
131 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); in reset_phy()
132 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); in reset_phy()
135 miiphy_reset(name, devadr); in reset_phy()
/openbmc/u-boot/board/Seagate/dockstar/
H A Ddockstar.c109 u16 devadr; in reset_phy() local
116 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { in reset_phy()
126 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); in reset_phy()
127 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in reset_phy()
129 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); in reset_phy()
130 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); in reset_phy()
133 miiphy_reset(name, devadr); in reset_phy()
/openbmc/u-boot/board/Synology/ds109/
H A Dds109.c149 u16 devadr; in reset_phy() local
156 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { in reset_phy()
165 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); in reset_phy()
166 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in reset_phy()
168 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); in reset_phy()
169 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); in reset_phy()
172 miiphy_reset(name, devadr); in reset_phy()
/openbmc/qemu/hw/usb/
H A Dhcd-dwc2.c310 p->devadr = devadr; in dwc2_handle_packet()
391 p->devadr = devadr; in dwc2_handle_packet()
509 dev = dwc2_find_device(s, p->devadr); in dwc2_async_packet_complete()
521 dwc2_handle_packet(s, p->devadr, dev, ep, p->index, false); in dwc2_async_packet_complete()
589 dev = dwc2_find_device(s, p->devadr); in dwc2_work_bh()
592 dwc2_handle_packet(s, p->devadr, dev, ep, p->index, true); in dwc2_work_bh()
617 uint32_t devadr, epnum, epdir, eptype, pid, len; in dwc2_enable_chan() local
624 devadr = get_field(hcchar, HCCHAR_DEVADDR); in dwc2_enable_chan()
631 dev = dwc2_find_device(s, devadr); in dwc2_enable_chan()
658 dwc2_handle_packet(s, devadr, dev, ep, index, true); in dwc2_enable_chan()
[all …]
H A Dhcd-dwc2.h47 uint32_t devadr; member
/openbmc/u-boot/drivers/net/pfe_eth/
H A Dpfe_mdio.c20 u32 devadr; in pfe_write_addr() local
25 devadr = ((dev_addr & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT); in pfe_write_addr()
28 reg_data = (EMAC_MII_DATA_TA | phy | devadr | reg_addr); in pfe_write_addr()