1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
29637c4b2SEvgeni Dobrev /*
39637c4b2SEvgeni Dobrev * Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
49637c4b2SEvgeni Dobrev *
59637c4b2SEvgeni Dobrev * Based on sheevaplug.c originally written by
69637c4b2SEvgeni Dobrev * Prafulla Wadaskar <prafulla@marvell.com>
79637c4b2SEvgeni Dobrev * (C) Copyright 2009
89637c4b2SEvgeni Dobrev * Marvell Semiconductor <www.marvell.com>
99637c4b2SEvgeni Dobrev */
109637c4b2SEvgeni Dobrev
119637c4b2SEvgeni Dobrev #include <common.h>
129637c4b2SEvgeni Dobrev #include <miiphy.h>
13c62db35dSSimon Glass #include <asm/mach-types.h>
149637c4b2SEvgeni Dobrev #include <asm/arch/soc.h>
159637c4b2SEvgeni Dobrev #include <asm/arch/mpp.h>
169637c4b2SEvgeni Dobrev #include <asm/arch/cpu.h>
179637c4b2SEvgeni Dobrev #include <asm/io.h>
189637c4b2SEvgeni Dobrev
199637c4b2SEvgeni Dobrev DECLARE_GLOBAL_DATA_PTR;
209637c4b2SEvgeni Dobrev
board_early_init_f(void)219637c4b2SEvgeni Dobrev int board_early_init_f(void)
229637c4b2SEvgeni Dobrev {
239637c4b2SEvgeni Dobrev /*
249637c4b2SEvgeni Dobrev * default gpio configuration
259637c4b2SEvgeni Dobrev */
269637c4b2SEvgeni Dobrev mvebu_config_gpio(NAS220_GE_OE_VAL_LOW, NAS220_GE_OE_VAL_HIGH,
279637c4b2SEvgeni Dobrev NAS220_GE_OE_LOW, NAS220_GE_OE_HIGH);
289637c4b2SEvgeni Dobrev
299637c4b2SEvgeni Dobrev /* Multi-Purpose Pins Functionality configuration */
309637c4b2SEvgeni Dobrev static const u32 kwmpp_config[] = {
319637c4b2SEvgeni Dobrev MPP0_NF_IO2,
329637c4b2SEvgeni Dobrev MPP1_NF_IO3,
339637c4b2SEvgeni Dobrev MPP2_NF_IO4,
349637c4b2SEvgeni Dobrev MPP3_NF_IO5,
359637c4b2SEvgeni Dobrev MPP4_NF_IO6,
369637c4b2SEvgeni Dobrev MPP5_NF_IO7,
379637c4b2SEvgeni Dobrev MPP6_SYSRST_OUTn,
389637c4b2SEvgeni Dobrev MPP7_SPI_SCn,
399637c4b2SEvgeni Dobrev MPP8_TW_SDA,
409637c4b2SEvgeni Dobrev MPP9_TW_SCK,
419637c4b2SEvgeni Dobrev MPP10_UART0_TXD,
429637c4b2SEvgeni Dobrev MPP11_UART0_RXD,
439637c4b2SEvgeni Dobrev MPP12_GPO,
449637c4b2SEvgeni Dobrev MPP13_GPIO,
459637c4b2SEvgeni Dobrev MPP14_GPIO,
469637c4b2SEvgeni Dobrev MPP15_SATA0_ACTn,
479637c4b2SEvgeni Dobrev MPP16_SATA1_ACTn,
489637c4b2SEvgeni Dobrev MPP17_SATA0_PRESENTn,
499637c4b2SEvgeni Dobrev MPP18_NF_IO0,
509637c4b2SEvgeni Dobrev MPP19_NF_IO1,
519637c4b2SEvgeni Dobrev MPP20_GPIO,
529637c4b2SEvgeni Dobrev MPP21_GPIO,
539637c4b2SEvgeni Dobrev MPP22_GPIO,
549637c4b2SEvgeni Dobrev MPP23_GPIO,
559637c4b2SEvgeni Dobrev MPP24_GPIO,
569637c4b2SEvgeni Dobrev MPP25_GPIO,
579637c4b2SEvgeni Dobrev MPP26_GPIO,
589637c4b2SEvgeni Dobrev MPP27_GPIO,
599637c4b2SEvgeni Dobrev MPP28_GPIO,
609637c4b2SEvgeni Dobrev MPP29_GPIO,
619637c4b2SEvgeni Dobrev MPP30_GPIO,
629637c4b2SEvgeni Dobrev MPP31_GPIO,
639637c4b2SEvgeni Dobrev MPP32_GPIO,
649637c4b2SEvgeni Dobrev MPP33_GPIO,
659637c4b2SEvgeni Dobrev MPP34_GPIO,
669637c4b2SEvgeni Dobrev MPP35_GPIO,
679637c4b2SEvgeni Dobrev 0
689637c4b2SEvgeni Dobrev };
699637c4b2SEvgeni Dobrev kirkwood_mpp_conf(kwmpp_config, NULL);
709637c4b2SEvgeni Dobrev return 0;
719637c4b2SEvgeni Dobrev }
729637c4b2SEvgeni Dobrev
board_init(void)739637c4b2SEvgeni Dobrev int board_init(void)
749637c4b2SEvgeni Dobrev {
759637c4b2SEvgeni Dobrev /*
769637c4b2SEvgeni Dobrev * arch number of board
779637c4b2SEvgeni Dobrev */
7892a1babfSTom Rini gd->bd->bi_arch_number = MACH_TYPE_RD88F6192_NAS;
799637c4b2SEvgeni Dobrev
809637c4b2SEvgeni Dobrev /* adress of boot parameters */
819637c4b2SEvgeni Dobrev gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
829637c4b2SEvgeni Dobrev
839637c4b2SEvgeni Dobrev return 0;
849637c4b2SEvgeni Dobrev }
859637c4b2SEvgeni Dobrev
869637c4b2SEvgeni Dobrev #ifdef CONFIG_RESET_PHY_R
879637c4b2SEvgeni Dobrev /* Configure and enable MV88E1116 PHY */
reset_phy(void)889637c4b2SEvgeni Dobrev void reset_phy(void)
899637c4b2SEvgeni Dobrev {
909637c4b2SEvgeni Dobrev u16 reg;
919637c4b2SEvgeni Dobrev u16 devadr;
929637c4b2SEvgeni Dobrev char *name = "egiga0";
939637c4b2SEvgeni Dobrev
949637c4b2SEvgeni Dobrev if (miiphy_set_current_dev(name))
959637c4b2SEvgeni Dobrev return;
969637c4b2SEvgeni Dobrev
979637c4b2SEvgeni Dobrev /* command to read PHY dev address */
989637c4b2SEvgeni Dobrev if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
999637c4b2SEvgeni Dobrev printf("Err..%s could not read PHY dev address\n", __func__);
1009637c4b2SEvgeni Dobrev return;
1019637c4b2SEvgeni Dobrev }
1029637c4b2SEvgeni Dobrev
1039637c4b2SEvgeni Dobrev /*
1049637c4b2SEvgeni Dobrev * Enable RGMII delay on Tx and Rx for CPU port
1059637c4b2SEvgeni Dobrev * Ref: sec 4.7.2 of chip datasheet
1069637c4b2SEvgeni Dobrev */
1079637c4b2SEvgeni Dobrev miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
1089637c4b2SEvgeni Dobrev miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
1099637c4b2SEvgeni Dobrev reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
1109637c4b2SEvgeni Dobrev miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
1119637c4b2SEvgeni Dobrev miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
1129637c4b2SEvgeni Dobrev
1139637c4b2SEvgeni Dobrev /* reset the phy */
1149637c4b2SEvgeni Dobrev miiphy_reset(name, devadr);
1159637c4b2SEvgeni Dobrev
1169637c4b2SEvgeni Dobrev printf("88E1116 Initialized on %s\n", name);
1179637c4b2SEvgeni Dobrev }
1189637c4b2SEvgeni Dobrev #endif /* CONFIG_RESET_PHY_R */
119