1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
255dd4ba5SPrafulla Wadaskar /*
355dd4ba5SPrafulla Wadaskar * (C) Copyright 2009
455dd4ba5SPrafulla Wadaskar * Marvell Semiconductor <www.marvell.com>
555dd4ba5SPrafulla Wadaskar * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
655dd4ba5SPrafulla Wadaskar */
755dd4ba5SPrafulla Wadaskar
855dd4ba5SPrafulla Wadaskar #include <common.h>
955dd4ba5SPrafulla Wadaskar #include <miiphy.h>
10c62db35dSSimon Glass #include <asm/mach-types.h>
11a7efd719SLei Wen #include <asm/arch/cpu.h>
123dc23f78SStefan Roese #include <asm/arch/soc.h>
1355dd4ba5SPrafulla Wadaskar #include <asm/arch/mpp.h>
1455dd4ba5SPrafulla Wadaskar #include "sheevaplug.h"
1555dd4ba5SPrafulla Wadaskar
1655dd4ba5SPrafulla Wadaskar DECLARE_GLOBAL_DATA_PTR;
1755dd4ba5SPrafulla Wadaskar
board_early_init_f(void)18754ae3fbSPrafulla Wadaskar int board_early_init_f(void)
1955dd4ba5SPrafulla Wadaskar {
2055dd4ba5SPrafulla Wadaskar /*
2155dd4ba5SPrafulla Wadaskar * default gpio configuration
2255dd4ba5SPrafulla Wadaskar * There are maximum 64 gpios controlled through 2 sets of registers
2355dd4ba5SPrafulla Wadaskar * the below configuration configures mainly initial LED status
2455dd4ba5SPrafulla Wadaskar */
25d5c5132fSStefan Roese mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
2655dd4ba5SPrafulla Wadaskar SHEEVAPLUG_OE_VAL_HIGH,
2755dd4ba5SPrafulla Wadaskar SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
2855dd4ba5SPrafulla Wadaskar
2955dd4ba5SPrafulla Wadaskar /* Multi-Purpose Pins Functionality configuration */
309d86f0c3SAlbert ARIBAUD static const u32 kwmpp_config[] = {
3155dd4ba5SPrafulla Wadaskar MPP0_NF_IO2,
3255dd4ba5SPrafulla Wadaskar MPP1_NF_IO3,
3355dd4ba5SPrafulla Wadaskar MPP2_NF_IO4,
3455dd4ba5SPrafulla Wadaskar MPP3_NF_IO5,
3555dd4ba5SPrafulla Wadaskar MPP4_NF_IO6,
3655dd4ba5SPrafulla Wadaskar MPP5_NF_IO7,
3755dd4ba5SPrafulla Wadaskar MPP6_SYSRST_OUTn,
3855dd4ba5SPrafulla Wadaskar MPP7_GPO,
3955dd4ba5SPrafulla Wadaskar MPP8_UART0_RTS,
4055dd4ba5SPrafulla Wadaskar MPP9_UART0_CTS,
4155dd4ba5SPrafulla Wadaskar MPP10_UART0_TXD,
4255dd4ba5SPrafulla Wadaskar MPP11_UART0_RXD,
4355dd4ba5SPrafulla Wadaskar MPP12_SD_CLK,
4455dd4ba5SPrafulla Wadaskar MPP13_SD_CMD,
4555dd4ba5SPrafulla Wadaskar MPP14_SD_D0,
4655dd4ba5SPrafulla Wadaskar MPP15_SD_D1,
4755dd4ba5SPrafulla Wadaskar MPP16_SD_D2,
4855dd4ba5SPrafulla Wadaskar MPP17_SD_D3,
4955dd4ba5SPrafulla Wadaskar MPP18_NF_IO0,
5055dd4ba5SPrafulla Wadaskar MPP19_NF_IO1,
5155dd4ba5SPrafulla Wadaskar MPP20_GPIO,
5255dd4ba5SPrafulla Wadaskar MPP21_GPIO,
5355dd4ba5SPrafulla Wadaskar MPP22_GPIO,
5455dd4ba5SPrafulla Wadaskar MPP23_GPIO,
5555dd4ba5SPrafulla Wadaskar MPP24_GPIO,
5655dd4ba5SPrafulla Wadaskar MPP25_GPIO,
5755dd4ba5SPrafulla Wadaskar MPP26_GPIO,
5855dd4ba5SPrafulla Wadaskar MPP27_GPIO,
5955dd4ba5SPrafulla Wadaskar MPP28_GPIO,
6055dd4ba5SPrafulla Wadaskar MPP29_TSMP9,
6155dd4ba5SPrafulla Wadaskar MPP30_GPIO,
6255dd4ba5SPrafulla Wadaskar MPP31_GPIO,
6355dd4ba5SPrafulla Wadaskar MPP32_GPIO,
6455dd4ba5SPrafulla Wadaskar MPP33_GPIO,
6555dd4ba5SPrafulla Wadaskar MPP34_GPIO,
6655dd4ba5SPrafulla Wadaskar MPP35_GPIO,
6755dd4ba5SPrafulla Wadaskar MPP36_GPIO,
6855dd4ba5SPrafulla Wadaskar MPP37_GPIO,
6955dd4ba5SPrafulla Wadaskar MPP38_GPIO,
7055dd4ba5SPrafulla Wadaskar MPP39_GPIO,
7155dd4ba5SPrafulla Wadaskar MPP40_GPIO,
7255dd4ba5SPrafulla Wadaskar MPP41_GPIO,
7355dd4ba5SPrafulla Wadaskar MPP42_GPIO,
7455dd4ba5SPrafulla Wadaskar MPP43_GPIO,
7555dd4ba5SPrafulla Wadaskar MPP44_GPIO,
7655dd4ba5SPrafulla Wadaskar MPP45_GPIO,
7755dd4ba5SPrafulla Wadaskar MPP46_GPIO,
7855dd4ba5SPrafulla Wadaskar MPP47_GPIO,
7955dd4ba5SPrafulla Wadaskar MPP48_GPIO,
8055dd4ba5SPrafulla Wadaskar MPP49_GPIO,
8155dd4ba5SPrafulla Wadaskar 0
8255dd4ba5SPrafulla Wadaskar };
8384683638SValentin Longchamp kirkwood_mpp_conf(kwmpp_config, NULL);
84754ae3fbSPrafulla Wadaskar return 0;
85754ae3fbSPrafulla Wadaskar }
8655dd4ba5SPrafulla Wadaskar
board_init(void)87754ae3fbSPrafulla Wadaskar int board_init(void)
88754ae3fbSPrafulla Wadaskar {
8955dd4ba5SPrafulla Wadaskar /*
9055dd4ba5SPrafulla Wadaskar * arch number of board
9155dd4ba5SPrafulla Wadaskar */
9255dd4ba5SPrafulla Wadaskar gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
9355dd4ba5SPrafulla Wadaskar
9455dd4ba5SPrafulla Wadaskar /* adress of boot parameters */
9596c5f081SStefan Roese gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
9655dd4ba5SPrafulla Wadaskar
9755dd4ba5SPrafulla Wadaskar return 0;
9855dd4ba5SPrafulla Wadaskar }
9955dd4ba5SPrafulla Wadaskar
10055dd4ba5SPrafulla Wadaskar #ifdef CONFIG_RESET_PHY_R
10155dd4ba5SPrafulla Wadaskar /* Configure and enable MV88E1116 PHY */
reset_phy(void)10255dd4ba5SPrafulla Wadaskar void reset_phy(void)
10355dd4ba5SPrafulla Wadaskar {
10455dd4ba5SPrafulla Wadaskar u16 reg;
10555dd4ba5SPrafulla Wadaskar u16 devadr;
10655dd4ba5SPrafulla Wadaskar char *name = "egiga0";
10755dd4ba5SPrafulla Wadaskar
10855dd4ba5SPrafulla Wadaskar if (miiphy_set_current_dev(name))
10955dd4ba5SPrafulla Wadaskar return;
11055dd4ba5SPrafulla Wadaskar
11155dd4ba5SPrafulla Wadaskar /* command to read PHY dev address */
11255dd4ba5SPrafulla Wadaskar if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
11355dd4ba5SPrafulla Wadaskar printf("Err..%s could not read PHY dev address\n",
11455dd4ba5SPrafulla Wadaskar __FUNCTION__);
11555dd4ba5SPrafulla Wadaskar return;
11655dd4ba5SPrafulla Wadaskar }
11755dd4ba5SPrafulla Wadaskar
11855dd4ba5SPrafulla Wadaskar /*
11955dd4ba5SPrafulla Wadaskar * Enable RGMII delay on Tx and Rx for CPU port
12055dd4ba5SPrafulla Wadaskar * Ref: sec 4.7.2 of chip datasheet
12155dd4ba5SPrafulla Wadaskar */
12255dd4ba5SPrafulla Wadaskar miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
12355dd4ba5SPrafulla Wadaskar miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
12455dd4ba5SPrafulla Wadaskar reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
12555dd4ba5SPrafulla Wadaskar miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
12655dd4ba5SPrafulla Wadaskar miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
12755dd4ba5SPrafulla Wadaskar
12855dd4ba5SPrafulla Wadaskar /* reset the phy */
12955dd4ba5SPrafulla Wadaskar miiphy_reset(name, devadr);
13055dd4ba5SPrafulla Wadaskar
13155dd4ba5SPrafulla Wadaskar printf("88E1116 Initialized on %s\n", name);
13255dd4ba5SPrafulla Wadaskar }
13355dd4ba5SPrafulla Wadaskar #endif /* CONFIG_RESET_PHY_R */
134