| /openbmc/u-boot/arch/arm/mach-omap2/am33xx/ |
| H A D | ti816x_emif4.c | 106 writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x120)); in ddr3_sw_levelling()
107 writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x1C4)); in ddr3_sw_levelling()
108 writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x268)); in ddr3_sw_levelling()
109 writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x30C)); in ddr3_sw_levelling()
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| H A D | chilisom.c | 70 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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| H A D | ddr.c | 368 writel(data->datawrsratio0, in config_ddr_data()
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| /openbmc/u-boot/board/phytec/pcm051/ |
| H A D | board.c | 65 .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
108 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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| /openbmc/u-boot/board/gumstix/pepper/ |
| H A D | board.c | 41 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
78 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
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| /openbmc/u-boot/board/isee/igep003x/ |
| H A D | board.c | 72 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
79 .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
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| /openbmc/u-boot/board/ti/am335x/ |
| H A D | board.c | 96 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
130 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
137 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
144 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
151 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
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| /openbmc/u-boot/board/compulab/cm_t335/ |
| H A D | spl.c | 34 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
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| /openbmc/u-boot/board/ti/ti816x/ |
| H A D | evm.c | 119 .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
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| /openbmc/u-boot/board/ti/ti814x/ |
| H A D | evm.c | 76 .datawrsratio0 = ((0x50<<10) | (0x50<<0)),
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| /openbmc/u-boot/board/BuR/brppt1/ |
| H A D | board.c | 43 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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| /openbmc/u-boot/board/silica/pengwyn/ |
| H A D | board.c | 31 .datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
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| /openbmc/u-boot/board/eets/pdu001/ |
| H A D | board.c | 166 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
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| /openbmc/u-boot/board/BuR/brxre1/ |
| H A D | board.c | 77 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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| /openbmc/u-boot/arch/arm/include/asm/arch-am33xx/ |
| H A D | ddr_defs.h | 305 unsigned long datawrsratio0; member
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| /openbmc/u-boot/board/tcl/sl50/ |
| H A D | board.c | 45 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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| /openbmc/u-boot/board/birdland/bav335x/ |
| H A D | board.c | 131 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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| /openbmc/u-boot/board/bosch/shc/ |
| H A D | board.c | 399 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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| /openbmc/u-boot/board/siemens/draco/ |
| H A D | board.c | 229 draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0; in board_init_ddr()
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| /openbmc/u-boot/board/siemens/rut/ |
| H A D | board.c | 62 .datawrsratio0 = 0xc1, in board_init_ddr()
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| /openbmc/u-boot/board/siemens/pxm2/ |
| H A D | board.c | 58 .datawrsratio0 = 0x4010040, in board_init_ddr()
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| /openbmc/u-boot/board/vscom/baltos/ |
| H A D | board.c | 130 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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