Searched refs:csr1 (Results 1 – 5 of 5) sorted by relevance
410 u32 csr0, csr1, csr2; in mtu3_config_ep() local428 csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot); in mtu3_config_ep()436 csr1 |= TX_TYPE(TYPE_BULK); in mtu3_config_ep()439 csr1 |= TX_TYPE(TYPE_ISO); in mtu3_config_ep()443 csr1 |= TX_TYPE(TYPE_INT); in mtu3_config_ep()452 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1); in mtu3_config_ep()464 csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot); in mtu3_config_ep()472 csr1 |= RX_TYPE(TYPE_BULK); in mtu3_config_ep()475 csr1 |= RX_TYPE(TYPE_ISO); in mtu3_config_ep()479 csr1 |= RX_TYPE(TYPE_INT); in mtu3_config_ep()[all …]
19 u32 csr1; /* power control/status register 2 */ member
484 u32 mac, csr1; in emac_mac_start() local494 csr1 = readl(adpt->csr + EMAC_EMAC_WRAPPER_CSR1); in emac_mac_start()516 csr1 |= FREQ_MODE; in emac_mac_start()519 csr1 &= ~FREQ_MODE; in emac_mac_start()558 writel_relaxed(csr1, adpt->csr + EMAC_EMAC_WRAPPER_CSR1); in emac_mac_start()
239 while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY)) in configure_clocks()244 while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY)) in configure_clocks()