1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2d0a768b1SPatrice Chotard /*
3d0a768b1SPatrice Chotard  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4d0a768b1SPatrice Chotard  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
5d0a768b1SPatrice Chotard  */
6d0a768b1SPatrice Chotard 
7d0a768b1SPatrice Chotard #ifndef __STM32_PWR_H_
8d0a768b1SPatrice Chotard 
9d0a768b1SPatrice Chotard /*
10d0a768b1SPatrice Chotard  * Offsets of some PWR registers
11d0a768b1SPatrice Chotard  */
12d0a768b1SPatrice Chotard #define PWR_CR1_ODEN			BIT(16)
13d0a768b1SPatrice Chotard #define PWR_CR1_ODSWEN			BIT(17)
14d0a768b1SPatrice Chotard #define PWR_CSR1_ODRDY			BIT(16)
15d0a768b1SPatrice Chotard #define PWR_CSR1_ODSWRDY		BIT(17)
16d0a768b1SPatrice Chotard 
17d0a768b1SPatrice Chotard struct stm32_pwr_regs {
18d0a768b1SPatrice Chotard 	u32 cr1;   /* power control register 1 */
19d0a768b1SPatrice Chotard 	u32 csr1;  /* power control/status register 2 */
20d0a768b1SPatrice Chotard 	u32 cr2;   /* power control register 2 */
21d0a768b1SPatrice Chotard 	u32 csr2;  /* power control/status register 2 */
22d0a768b1SPatrice Chotard };
23d0a768b1SPatrice Chotard 
24d0a768b1SPatrice Chotard #endif /* __STM32_PWR_H_ */
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