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Searched refs:con1 (Results 1 – 21 of 21) sorted by relevance

/openbmc/u-boot/drivers/adc/
H A Dexynos-adc.c49 cfg = readl(&regs->con1); in exynos_adc_start_channel()
50 writel(cfg | ADC_V2_CON1_STC_EN, &regs->con1); in exynos_adc_start_channel()
64 cfg = readl(&regs->con1); in exynos_adc_stop()
67 writel(cfg, &regs->con1); in exynos_adc_stop()
87 writel(ADC_V2_CON1_SOFT_RESET, &regs->con1); in exynos_adc_probe()
/openbmc/u-boot/drivers/net/
H A Dpic32_eth.c63 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_mii_init()
70 writel(ETHCON_ON, &ectl_p->con1.set); in pic32_mii_init()
238 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_ctrl_reset()
245 writel(ETHCON_BUFCDEC, &ectl_p->con1.set); in pic32_ctrl_reset()
269 writel(ETHCON_ON, &ectl_p->con1.set); in pic32_ctrl_reset()
296 writel(ETHCON_BUFCDEC, &ectl_p->con1.set); in pic32_rx_desc_init()
318 writel(ETHCON_RXEN, &ectl_p->con1.set); in pic32_rx_desc_init()
355 if (readl(&ectl_p->con1.raw) & ETHCON_ON) in pic32_eth_stop()
362 writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_eth_stop()
373 writel(ETHCON_ON, &ectl_p->con1.clr); in pic32_eth_stop()
[all …]
H A Dpic32_eth.h14 struct pic32_reg_atomic con1; /* 0x00 */ member
/openbmc/u-boot/drivers/clk/exynos/
H A Dclk-pll.c19 unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq) in pll145x_get_rate() argument
21 unsigned long pll_con1 = readl(con1); in pll145x_get_rate()
H A Dclk-pll.h8 unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk322x.c58 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
60 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
65 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
70 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
73 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
201 con = readl(&pll->con1); in rkclk_pll_get_rate()
H A Dclk_rk3128.c55 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
57 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
62 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
67 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
70 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
268 con = readl(&pll->con1); in rkclk_pll_get_rate()
H A Dclk_rk3036.c62 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
67 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
72 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
200 con = readl(&pll->con1); in rkclk_pll_get_rate()
H A Dclk_rv1108.c94 rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK, in rkclk_set_pll()
121 uint32_t con0, con1, con3; in rkclk_pll_get_rate() local
130 con1 = readl(&pll->con1); in rkclk_pll_get_rate()
132 postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT; in rkclk_pll_get_rate()
133 postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; in rkclk_pll_get_rate()
134 refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK; in rkclk_pll_get_rate()
H A Dclk_rk3368.c77 con = readl(&pll->con1); in rkclk_pll_get_rate()
106 writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1); in rkclk_set_pll()
119 while (!(readl(&pll->con1) & PLL_LOCK_STA)) in rkclk_set_pll()
H A Dclk_rk3188.c106 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
248 con = readl(&pll->con1); in rkclk_pll_get_rate()
H A Dclk_rk3288.c164 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
560 con = readl(&pll->con1); in rkclk_pll_get_rate()
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dadc.h58 unsigned int con1; member
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3188.h36 u32 con1; member
H A Dcru_rk3368.h26 unsigned int con1; member
H A Dcru_rk3036.h35 unsigned int con1; member
H A Dcru_rk322x.h36 unsigned int con1; member
H A Dcru_rk3128.h36 unsigned int con1; member
H A Dcru_rk3288.h37 u32 con1; member
H A Dcru_rv1108.h28 unsigned int con1; member
/openbmc/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c336 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkdclk_init()
342 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkdclk_init()
347 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkdclk_init()