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Searched refs:con1 (Results 1 – 25 of 30) sorted by relevance

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/openbmc/linux/drivers/iio/adc/
H A Dexynos_adc.c231 u32 con1; in exynos_adc_v1_init_hw() local
237 con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN; in exynos_adc_v1_init_hw()
240 con1 |= ADC_V1_CON_RES; in exynos_adc_v1_init_hw()
241 writel(con1, ADC_V1_CON(info->regs)); in exynos_adc_v1_init_hw()
267 u32 con1; in exynos_adc_v1_start_conv() local
271 con1 = readl(ADC_V1_CON(info->regs)); in exynos_adc_v1_start_conv()
272 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); in exynos_adc_v1_start_conv()
313 u32 con1; in exynos_adc_s3c2416_start_conv() local
316 con1 = readl(ADC_V1_CON(info->regs)); in exynos_adc_s3c2416_start_conv()
317 con1 |= ADC_S3C2416_CON_RES_SEL; in exynos_adc_s3c2416_start_conv()
[all …]
/openbmc/linux/drivers/pwm/
H A Dpwm-mtk-disp.c34 unsigned int con1; member
153 mtk_disp_pwm_update_bits(mdp, mdp->data->con1, in mtk_disp_pwm_apply()
179 u32 clk_div, pwm_en, con0, con1; in mtk_disp_pwm_get_state() local
207 con1 = readl(mdp->base + mdp->data->con1); in mtk_disp_pwm_get_state()
211 period = FIELD_GET(PWM_PERIOD_MASK, con1); in mtk_disp_pwm_get_state()
217 high_width = FIELD_GET(PWM_HIGH_WIDTH_MASK, con1); in mtk_disp_pwm_get_state()
282 .con1 = 0xac,
292 .con1 = 0x14,
302 .con1 = 0x1c,
/openbmc/u-boot/drivers/adc/
H A Dexynos-adc.c49 cfg = readl(&regs->con1); in exynos_adc_start_channel()
50 writel(cfg | ADC_V2_CON1_STC_EN, &regs->con1); in exynos_adc_start_channel()
64 cfg = readl(&regs->con1); in exynos_adc_stop()
67 writel(cfg, &regs->con1); in exynos_adc_stop()
87 writel(ADC_V2_CON1_SOFT_RESET, &regs->con1); in exynos_adc_probe()
/openbmc/u-boot/drivers/net/
H A Dpic32_eth.c63 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_mii_init()
70 writel(ETHCON_ON, &ectl_p->con1.set); in pic32_mii_init()
238 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_ctrl_reset()
245 writel(ETHCON_BUFCDEC, &ectl_p->con1.set); in pic32_ctrl_reset()
269 writel(ETHCON_ON, &ectl_p->con1.set); in pic32_ctrl_reset()
296 writel(ETHCON_BUFCDEC, &ectl_p->con1.set); in pic32_rx_desc_init()
318 writel(ETHCON_RXEN, &ectl_p->con1.set); in pic32_rx_desc_init()
355 if (readl(&ectl_p->con1.raw) & ETHCON_ON) in pic32_eth_stop()
362 writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_eth_stop()
373 writel(ETHCON_ON, &ectl_p->con1.clr); in pic32_eth_stop()
[all …]
H A Dpic32_eth.h14 struct pic32_reg_atomic con1; /* 0x00 */ member
/openbmc/linux/drivers/clk/samsung/
H A Dclk-pll.c660 u32 con0, con1; in samsung_pll45xx_set_rate()
671 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
673 if (!(samsung_pll45xx_mp_change(con0, con1, rate))) { in samsung_pll45xx_set_rate()
691 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
692 con1 &= ~(PLL45XX_AFC_MASK << PLL45XX_AFC_SHIFT); in samsung_pll45xx_set_rate()
693 con1 |= (rate->afc << PLL45XX_AFC_SHIFT); in samsung_pll45xx_set_rate()
708 writel_relaxed(con1, pll->con_reg + 0x4); in samsung_pll45xx_set_rate()
797 u32 con0, con1, lock; in samsung_pll46xx_set_rate()
808 con1 = readl_relaxed(pll->con_reg + 0x4); in samsung_pll46xx_set_rate()
810 if (!(samsung_pll46xx_mpk_change(con0, con1, rat in samsung_pll46xx_set_rate()
655 u32 con0, con1; samsung_pll45xx_set_rate() local
792 u32 con0, con1, lock; samsung_pll46xx_set_rate() local
1125 u32 con0, con1; samsung_pll2650x_set_rate() local
[all...]
/openbmc/u-boot/drivers/clk/exynos/
H A Dclk-pll.c19 unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq) in pll145x_get_rate() argument
21 unsigned long pll_con1 = readl(con1); in pll145x_get_rate()
H A Dclk-pll.h8 unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk322x.c58 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
60 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
65 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
70 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
73 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
201 con = readl(&pll->con1); in rkclk_pll_get_rate()
H A Dclk_rk3128.c55 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
57 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
62 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
67 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
70 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
268 con = readl(&pll->con1); in rkclk_pll_get_rate()
H A Dclk_rv1108.c94 rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK, in rkclk_set_pll()
121 uint32_t con0, con1, con3; in rkclk_pll_get_rate() local
130 con1 = readl(&pll->con1); in rkclk_pll_get_rate()
132 postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT; in rkclk_pll_get_rate()
133 postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; in rkclk_pll_get_rate()
134 refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK; in rkclk_pll_get_rate()
H A Dclk_rk3036.c62 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
67 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
72 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
200 con = readl(&pll->con1); in rkclk_pll_get_rate()
H A Dclk_rk3368.c77 con = readl(&pll->con1); in rkclk_pll_get_rate()
106 writel((div->nf - 1) << PLL_NF_SHIFT, &pll->con1); in rkclk_set_pll()
119 while (!(readl(&pll->con1) & PLL_LOCK_STA)) in rkclk_set_pll()
/openbmc/linux/drivers/media/dvb-frontends/
H A Ditd1000.c120 u8 con1 = itd1000_read_reg(state, CON1) & 0xfd; in itd1000_set_lpf_bw() local
128 itd1000_write_reg(state, CON1, con1 | (1 << 1)); in itd1000_set_lpf_bw()
139 itd1000_write_reg(state, CON1, con1 | (0 << 1)); in itd1000_set_lpf_bw()
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dadc.h58 unsigned int con1; member
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3188.h36 u32 con1; member
H A Dcru_rk3368.h26 unsigned int con1; member
H A Dcru_rk3036.h35 unsigned int con1; member
H A Dcru_rk322x.h36 unsigned int con1; member
H A Dcru_rk3128.h36 unsigned int con1; member
H A Dcru_rk3288.h37 u32 con1; member
H A Dcru_rv1108.h28 unsigned int con1; member
/openbmc/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c336 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkdclk_init()
342 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkdclk_init()
347 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkdclk_init()
/openbmc/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-dai-etdm.c91 unsigned int con1; member
202 etdm_reg->con1 = ETDM_IN1_CON1; in get_etdm_reg()
210 etdm_reg->con1 = ETDM_IN2_CON1; in get_etdm_reg()
218 etdm_reg->con1 = ETDM_OUT1_CON1; in get_etdm_reg()
226 etdm_reg->con1 = ETDM_OUT2_CON1; in get_etdm_reg()
235 etdm_reg->con1 = ETDM_OUT3_CON1; in get_etdm_reg()
1733 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); in mtk_dai_etdm_in_configure()
1858 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); in mtk_dai_etdm_out_configure()
1938 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); in mtk_dai_etdm_mclk_configure()
/openbmc/linux/sound/soc/mediatek/mt8188/
H A Dmt8188-dai-etdm.c82 unsigned int con1; member
161 etdm_reg->con1 = ETDM_IN1_CON1; in get_etdm_reg()
169 etdm_reg->con1 = ETDM_IN2_CON1; in get_etdm_reg()
177 etdm_reg->con1 = ETDM_OUT1_CON1; in get_etdm_reg()
185 etdm_reg->con1 = ETDM_OUT2_CON1; in get_etdm_reg()
194 etdm_reg->con1 = ETDM_OUT3_CON1; in get_etdm_reg()
419 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); in mtk_dai_etdm_enable_mclk()
1938 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); in mtk_dai_etdm_in_configure()
2057 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); in mtk_dai_etdm_out_configure()

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