1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2166097e8SThomas Abraham /* 3166097e8SThomas Abraham * Exynos PLL helper functions for clock drivers. 4166097e8SThomas Abraham * Copyright (C) 2016 Samsung Electronics 5166097e8SThomas Abraham * Thomas Abraham <thomas.ab@samsung.com> 6166097e8SThomas Abraham */ 7166097e8SThomas Abraham 8166097e8SThomas Abraham #include <common.h> 9166097e8SThomas Abraham #include <asm/io.h> 10166097e8SThomas Abraham #include <div64.h> 11166097e8SThomas Abraham 12166097e8SThomas Abraham #define PLL145X_MDIV_SHIFT 16 13166097e8SThomas Abraham #define PLL145X_MDIV_MASK 0x3ff 14166097e8SThomas Abraham #define PLL145X_PDIV_SHIFT 8 15166097e8SThomas Abraham #define PLL145X_PDIV_MASK 0x3f 16166097e8SThomas Abraham #define PLL145X_SDIV_SHIFT 0 17166097e8SThomas Abraham #define PLL145X_SDIV_MASK 0x7 18166097e8SThomas Abraham pll145x_get_rate(unsigned int * con1,unsigned long fin_freq)19166097e8SThomas Abrahamunsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq) 20166097e8SThomas Abraham { 21166097e8SThomas Abraham unsigned long pll_con1 = readl(con1); 22166097e8SThomas Abraham unsigned long mdiv, sdiv, pdiv; 23166097e8SThomas Abraham uint64_t fvco = fin_freq; 24166097e8SThomas Abraham 25166097e8SThomas Abraham mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK; 26166097e8SThomas Abraham pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK; 27166097e8SThomas Abraham sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK; 28166097e8SThomas Abraham 29166097e8SThomas Abraham fvco *= mdiv; 30166097e8SThomas Abraham do_div(fvco, (pdiv << sdiv)); 31166097e8SThomas Abraham return (unsigned long)fvco; 32166097e8SThomas Abraham } 33