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Searched refs:clksel (Results 1 – 25 of 26) sorted by relevance

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/openbmc/linux/drivers/mmc/host/
H A Ddw_mmc-exynos.c143 u32 clksel; in dw_mci_exynos_set_clksel_timing() local
150 clksel = mci_readl(host, CLKSEL); in dw_mci_exynos_set_clksel_timing()
152 clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing; in dw_mci_exynos_set_clksel_timing()
217 u32 clksel; in dw_mci_exynos_resume_noirq() local
325 clksel = priv->ddr_timing; in dw_mci_exynos_set_ios()
340 clksel = priv->sdr_timing; in dw_mci_exynos_set_ios()
421 u32 clksel; in dw_mci_exynos_set_clksmpl() local
430 clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample); in dw_mci_exynos_set_clksmpl()
442 u32 clksel; in dw_mci_exynos_move_next_clksmpl() local
452 sample = (clksel + 1) & 0x7; in dw_mci_exynos_move_next_clksmpl()
[all …]
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-cpu.c105 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; in rockchip_cpuclk_set_dividers() local
107 if (!clksel->reg) in rockchip_cpuclk_set_dividers()
111 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_dividers()
112 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
123 const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i]; in rockchip_cpuclk_set_pre_muxs() local
125 if (!clksel->reg) in rockchip_cpuclk_set_pre_muxs()
129 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_pre_muxs()
130 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_pre_muxs()
143 if (!clksel->reg) in rockchip_cpuclk_set_post_muxs()
147 __func__, clksel->reg, clksel->val); in rockchip_cpuclk_set_post_muxs()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Dti,clksel.yaml4 $id: http://devicetree.org/schemas/clock/ti/ti,clksel.yaml#
7 title: TI clksel clock
18 const: ti,clksel
47 compatible = "ti,clksel";
/openbmc/linux/drivers/clocksource/
H A Dtimer-cadence-ttc.c476 int clksel, ret; in ttc_timer_probe() local
504 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
505 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
506 clk_cs = of_clk_get(timer, clksel); in ttc_timer_probe()
512 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); in ttc_timer_probe()
513 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK); in ttc_timer_probe()
514 clk_ce = of_clk_get(timer, clksel); in ttc_timer_probe()
/openbmc/qemu/hw/char/
H A Domap_uart.c41 uint8_t clksel; member
50 s->clksel = 0; in omap_uart_reset()
90 return s->clksel; in omap_uart_read()
131 s->clksel = value & 1; in omap_uart_write()
/openbmc/qemu/hw/arm/
H A Domap2.c1034 uint32_t clksel[8]; member
1130 return s->clksel[0]; in omap_prcm_read()
1180 return s->clksel[1]; in omap_prcm_read()
1182 return s->clksel[2]; in omap_prcm_read()
1212 return s->clksel[3]; in omap_prcm_read()
1770 s->clksel[0] = 0x01; in omap_prcm_reset()
1773 s->clksel[3] = 0x01; in omap_prcm_reset()
1774 s->clksel[4] = 0; in omap_prcm_reset()
1775 s->clksel[7] = 0x0121; in omap_prcm_reset()
1806 s->clksel[5] = 0; in omap_prcm_coldreset()
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap36xx-omap3430es2plus-clocks.dtsi9 compatible = "ti,clksel";
24 compatible = "ti,clksel";
54 compatible = "ti,clksel";
85 compatible = "ti,clksel";
172 compatible = "ti,clksel";
194 compatible = "ti,clksel";
H A Domap34xx-omap36xx-clocks.dtsi17 compatible = "ti,clksel";
65 compatible = "ti,clksel";
105 compatible = "ti,clksel";
160 compatible = "ti,clksel";
228 compatible = "ti,clksel";
252 compatible = "ti,clksel";
H A Domap3430es1-clocks.dtsi50 compatible = "ti,clksel";
81 compatible = "ti,clksel";
121 compatible = "ti,clksel";
174 compatible = "ti,clksel";
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi138 compatible = "ti,clksel";
153 compatible = "ti,clksel";
168 compatible = "ti,clksel";
183 compatible = "ti,clksel";
H A Dam35xx-clocks.dtsi66 compatible = "ti,clksel";
101 compatible = "ti,clksel";
H A Domap3xxx-clocks.dtsi83 compatible = "ti,clksel";
120 compatible = "ti,clksel";
259 compatible = "ti,clksel";
429 compatible = "ti,clksel";
471 compatible = "ti,clksel";
603 compatible = "ti,clksel";
666 compatible = "ti,clksel";
709 compatible = "ti,clksel";
734 compatible = "ti,clksel";
914 compatible = "ti,clksel";
[all …]
H A Domap36xx-clocks.dtsi62 compatible = "ti,clksel";
H A Dam33xx-clocks.dtsi108 compatible = "ti,clksel";
566 compatible = "ti,clksel";
571 gfx_fclk_clksel_ck: clock-gfx-fclk-clksel {
589 compatible = "ti,clksel";
/openbmc/linux/arch/arm/mach-imx/
H A Dmach-imx6q.c85 u32 clksel; in imx6q_1588_init() local
118 clksel = clk_is_match(ptp_clk, enet_ref) ? in imx6q_1588_init()
125 clksel); in imx6q_1588_init()
/openbmc/linux/drivers/clk/
H A Dclk-qoriq.c59 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS]; member
852 u32 clksel; in mux_set_parent() local
857 clksel = hwc->parent_to_clksel[idx]; in mux_set_parent()
866 u32 clksel; in mux_get_parent() local
871 ret = hwc->clksel_to_parent[clksel]; in mux_get_parent()
900 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID)) in get_pll_div()
903 pll = hwc->info->clksel[idx].pll; in get_pll_div()
904 div = hwc->info->clksel[idx].div; in get_pll_div()
937 if (hwc->info->clksel[i].flags & CLKSEL_80PCT && in create_mux_common()
976 u32 clksel; in create_one_cmux() local
[all …]
/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_lvds.c138 u32 clksel; member
143 u32 clksel, bool dot_clock_only) in rcar_lvds_d3_e3_pll_calc() argument
251 pll->clksel = clksel; in rcar_lvds_d3_e3_pll_calc()
285 lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT in rcar_lvds_pll_setup_d3_e3()
/openbmc/qemu/hw/display/
H A Dblizzard.c38 uint8_t clksel; member
202 s->clksel = 0x00; in blizzard_reset()
302 return s->clksel; in blizzard_reg_read()
509 s->clksel = value & 0xff; in blizzard_reg_write()
/openbmc/u-boot/include/
H A Ddwmmc.h175 void (*clksel)(struct dwmci_host *host); member
/openbmc/u-boot/drivers/mmc/
H A Dsocfpga_dw_mmc.c118 host->clksel = socfpga_dwmci_clksel; in socfpga_dwmmc_ofdata_to_platdata()
H A Ddw_mmc.c469 if (host->clksel)
470 host->clksel(host);
H A Dexynos_dw_mmc.c122 host->clksel = exynos_dwmci_clksel; in exynos_dwmci_core_init()
/openbmc/qemu/tests/qtest/
H A Dnpcm7xx_pwm-test.c291 uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL); in read_pclk() local
297 switch (CPUCKSEL(clksel)) { in read_pclk()
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dcpu.h401 u32 clksel; /* 0xd40 */ member
/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dclock.c613 clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel); in prcm_init()

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