1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree Source for AM33xx clock data 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2013 Texas Instruments, Inc. 6*724ba675SRob Herring */ 7*724ba675SRob Herring&scm_clocks { 8*724ba675SRob Herring sys_clkin_ck: clock-sys-clkin-22@40 { 9*724ba675SRob Herring #clock-cells = <0>; 10*724ba675SRob Herring compatible = "ti,mux-clock"; 11*724ba675SRob Herring clock-output-names = "sys_clkin_ck"; 12*724ba675SRob Herring clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; 13*724ba675SRob Herring ti,bit-shift = <22>; 14*724ba675SRob Herring reg = <0x0040>; 15*724ba675SRob Herring }; 16*724ba675SRob Herring 17*724ba675SRob Herring adc_tsc_fck: clock-adc-tsc-fck { 18*724ba675SRob Herring #clock-cells = <0>; 19*724ba675SRob Herring compatible = "fixed-factor-clock"; 20*724ba675SRob Herring clock-output-names = "adc_tsc_fck"; 21*724ba675SRob Herring clocks = <&sys_clkin_ck>; 22*724ba675SRob Herring clock-mult = <1>; 23*724ba675SRob Herring clock-div = <1>; 24*724ba675SRob Herring }; 25*724ba675SRob Herring 26*724ba675SRob Herring dcan0_fck: clock-dcan0-fck { 27*724ba675SRob Herring #clock-cells = <0>; 28*724ba675SRob Herring compatible = "fixed-factor-clock"; 29*724ba675SRob Herring clock-output-names = "dcan0_fck"; 30*724ba675SRob Herring clocks = <&sys_clkin_ck>; 31*724ba675SRob Herring clock-mult = <1>; 32*724ba675SRob Herring clock-div = <1>; 33*724ba675SRob Herring }; 34*724ba675SRob Herring 35*724ba675SRob Herring dcan1_fck: clock-dcan1-fck { 36*724ba675SRob Herring #clock-cells = <0>; 37*724ba675SRob Herring compatible = "fixed-factor-clock"; 38*724ba675SRob Herring clock-output-names = "dcan1_fck"; 39*724ba675SRob Herring clocks = <&sys_clkin_ck>; 40*724ba675SRob Herring clock-mult = <1>; 41*724ba675SRob Herring clock-div = <1>; 42*724ba675SRob Herring }; 43*724ba675SRob Herring 44*724ba675SRob Herring mcasp0_fck: clock-mcasp0-fck { 45*724ba675SRob Herring #clock-cells = <0>; 46*724ba675SRob Herring compatible = "fixed-factor-clock"; 47*724ba675SRob Herring clock-output-names = "mcasp0_fck"; 48*724ba675SRob Herring clocks = <&sys_clkin_ck>; 49*724ba675SRob Herring clock-mult = <1>; 50*724ba675SRob Herring clock-div = <1>; 51*724ba675SRob Herring }; 52*724ba675SRob Herring 53*724ba675SRob Herring mcasp1_fck: clock-mcasp1-fck { 54*724ba675SRob Herring #clock-cells = <0>; 55*724ba675SRob Herring compatible = "fixed-factor-clock"; 56*724ba675SRob Herring clock-output-names = "mcasp1_fck"; 57*724ba675SRob Herring clocks = <&sys_clkin_ck>; 58*724ba675SRob Herring clock-mult = <1>; 59*724ba675SRob Herring clock-div = <1>; 60*724ba675SRob Herring }; 61*724ba675SRob Herring 62*724ba675SRob Herring smartreflex0_fck: clock-smartreflex0-fck { 63*724ba675SRob Herring #clock-cells = <0>; 64*724ba675SRob Herring compatible = "fixed-factor-clock"; 65*724ba675SRob Herring clock-output-names = "smartreflex0_fck"; 66*724ba675SRob Herring clocks = <&sys_clkin_ck>; 67*724ba675SRob Herring clock-mult = <1>; 68*724ba675SRob Herring clock-div = <1>; 69*724ba675SRob Herring }; 70*724ba675SRob Herring 71*724ba675SRob Herring smartreflex1_fck: clock-smartreflex1-fck { 72*724ba675SRob Herring #clock-cells = <0>; 73*724ba675SRob Herring compatible = "fixed-factor-clock"; 74*724ba675SRob Herring clock-output-names = "smartreflex1_fck"; 75*724ba675SRob Herring clocks = <&sys_clkin_ck>; 76*724ba675SRob Herring clock-mult = <1>; 77*724ba675SRob Herring clock-div = <1>; 78*724ba675SRob Herring }; 79*724ba675SRob Herring 80*724ba675SRob Herring sha0_fck: clock-sha0-fck { 81*724ba675SRob Herring #clock-cells = <0>; 82*724ba675SRob Herring compatible = "fixed-factor-clock"; 83*724ba675SRob Herring clock-output-names = "sha0_fck"; 84*724ba675SRob Herring clocks = <&sys_clkin_ck>; 85*724ba675SRob Herring clock-mult = <1>; 86*724ba675SRob Herring clock-div = <1>; 87*724ba675SRob Herring }; 88*724ba675SRob Herring 89*724ba675SRob Herring aes0_fck: clock-aes0-fck { 90*724ba675SRob Herring #clock-cells = <0>; 91*724ba675SRob Herring compatible = "fixed-factor-clock"; 92*724ba675SRob Herring clock-output-names = "aes0_fck"; 93*724ba675SRob Herring clocks = <&sys_clkin_ck>; 94*724ba675SRob Herring clock-mult = <1>; 95*724ba675SRob Herring clock-div = <1>; 96*724ba675SRob Herring }; 97*724ba675SRob Herring 98*724ba675SRob Herring rng_fck: clock-rng-fck { 99*724ba675SRob Herring #clock-cells = <0>; 100*724ba675SRob Herring compatible = "fixed-factor-clock"; 101*724ba675SRob Herring clock-output-names = "rng_fck"; 102*724ba675SRob Herring clocks = <&sys_clkin_ck>; 103*724ba675SRob Herring clock-mult = <1>; 104*724ba675SRob Herring clock-div = <1>; 105*724ba675SRob Herring }; 106*724ba675SRob Herring 107*724ba675SRob Herring clock@664 { 108*724ba675SRob Herring compatible = "ti,clksel"; 109*724ba675SRob Herring reg = <0x664>; 110*724ba675SRob Herring #clock-cells = <2>; 111*724ba675SRob Herring #address-cells = <0>; 112*724ba675SRob Herring 113*724ba675SRob Herring ehrpwm0_tbclk: clock-ehrpwm0-tbclk { 114*724ba675SRob Herring #clock-cells = <0>; 115*724ba675SRob Herring compatible = "ti,gate-clock"; 116*724ba675SRob Herring clock-output-names = "ehrpwm0_tbclk"; 117*724ba675SRob Herring clocks = <&l4ls_gclk>; 118*724ba675SRob Herring ti,bit-shift = <0>; 119*724ba675SRob Herring }; 120*724ba675SRob Herring 121*724ba675SRob Herring ehrpwm1_tbclk: clock-ehrpwm1-tbclk { 122*724ba675SRob Herring #clock-cells = <0>; 123*724ba675SRob Herring compatible = "ti,gate-clock"; 124*724ba675SRob Herring clock-output-names = "ehrpwm1_tbclk"; 125*724ba675SRob Herring clocks = <&l4ls_gclk>; 126*724ba675SRob Herring ti,bit-shift = <1>; 127*724ba675SRob Herring }; 128*724ba675SRob Herring 129*724ba675SRob Herring ehrpwm2_tbclk: clock-ehrpwm2-tbclk { 130*724ba675SRob Herring #clock-cells = <0>; 131*724ba675SRob Herring compatible = "ti,gate-clock"; 132*724ba675SRob Herring clock-output-names = "ehrpwm2_tbclk"; 133*724ba675SRob Herring clocks = <&l4ls_gclk>; 134*724ba675SRob Herring ti,bit-shift = <2>; 135*724ba675SRob Herring }; 136*724ba675SRob Herring }; 137*724ba675SRob Herring}; 138*724ba675SRob Herring&prcm_clocks { 139*724ba675SRob Herring clk_32768_ck: clock-clk-32768 { 140*724ba675SRob Herring #clock-cells = <0>; 141*724ba675SRob Herring compatible = "fixed-clock"; 142*724ba675SRob Herring clock-output-names = "clk_32768_ck"; 143*724ba675SRob Herring clock-frequency = <32768>; 144*724ba675SRob Herring }; 145*724ba675SRob Herring 146*724ba675SRob Herring clk_rc32k_ck: clock-clk-rc32k { 147*724ba675SRob Herring #clock-cells = <0>; 148*724ba675SRob Herring compatible = "fixed-clock"; 149*724ba675SRob Herring clock-output-names = "clk_rc32k_ck"; 150*724ba675SRob Herring clock-frequency = <32000>; 151*724ba675SRob Herring }; 152*724ba675SRob Herring 153*724ba675SRob Herring virt_19200000_ck: clock-virt-19200000 { 154*724ba675SRob Herring #clock-cells = <0>; 155*724ba675SRob Herring compatible = "fixed-clock"; 156*724ba675SRob Herring clock-output-names = "virt_19200000_ck"; 157*724ba675SRob Herring clock-frequency = <19200000>; 158*724ba675SRob Herring }; 159*724ba675SRob Herring 160*724ba675SRob Herring virt_24000000_ck: clock-virt-24000000 { 161*724ba675SRob Herring #clock-cells = <0>; 162*724ba675SRob Herring compatible = "fixed-clock"; 163*724ba675SRob Herring clock-output-names = "virt_24000000_ck"; 164*724ba675SRob Herring clock-frequency = <24000000>; 165*724ba675SRob Herring }; 166*724ba675SRob Herring 167*724ba675SRob Herring virt_25000000_ck: clock-virt-25000000 { 168*724ba675SRob Herring #clock-cells = <0>; 169*724ba675SRob Herring compatible = "fixed-clock"; 170*724ba675SRob Herring clock-output-names = "virt_25000000_ck"; 171*724ba675SRob Herring clock-frequency = <25000000>; 172*724ba675SRob Herring }; 173*724ba675SRob Herring 174*724ba675SRob Herring virt_26000000_ck: clock-virt-26000000 { 175*724ba675SRob Herring #clock-cells = <0>; 176*724ba675SRob Herring compatible = "fixed-clock"; 177*724ba675SRob Herring clock-output-names = "virt_26000000_ck"; 178*724ba675SRob Herring clock-frequency = <26000000>; 179*724ba675SRob Herring }; 180*724ba675SRob Herring 181*724ba675SRob Herring tclkin_ck: clock-tclkin { 182*724ba675SRob Herring #clock-cells = <0>; 183*724ba675SRob Herring compatible = "fixed-clock"; 184*724ba675SRob Herring clock-output-names = "tclkin_ck"; 185*724ba675SRob Herring clock-frequency = <12000000>; 186*724ba675SRob Herring }; 187*724ba675SRob Herring 188*724ba675SRob Herring dpll_core_ck: clock@490 { 189*724ba675SRob Herring #clock-cells = <0>; 190*724ba675SRob Herring compatible = "ti,am3-dpll-core-clock"; 191*724ba675SRob Herring clock-output-names = "dpll_core_ck"; 192*724ba675SRob Herring clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 193*724ba675SRob Herring reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>; 194*724ba675SRob Herring }; 195*724ba675SRob Herring 196*724ba675SRob Herring dpll_core_x2_ck: clock-dpll-core-x2 { 197*724ba675SRob Herring #clock-cells = <0>; 198*724ba675SRob Herring compatible = "ti,am3-dpll-x2-clock"; 199*724ba675SRob Herring clock-output-names = "dpll_core_x2_ck"; 200*724ba675SRob Herring clocks = <&dpll_core_ck>; 201*724ba675SRob Herring }; 202*724ba675SRob Herring 203*724ba675SRob Herring dpll_core_m4_ck: clock-dpll-core-m4@480 { 204*724ba675SRob Herring #clock-cells = <0>; 205*724ba675SRob Herring compatible = "ti,divider-clock"; 206*724ba675SRob Herring clock-output-names = "dpll_core_m4_ck"; 207*724ba675SRob Herring clocks = <&dpll_core_x2_ck>; 208*724ba675SRob Herring ti,max-div = <31>; 209*724ba675SRob Herring reg = <0x0480>; 210*724ba675SRob Herring ti,index-starts-at-one; 211*724ba675SRob Herring }; 212*724ba675SRob Herring 213*724ba675SRob Herring dpll_core_m5_ck: clock-dpll-core-m5@484 { 214*724ba675SRob Herring #clock-cells = <0>; 215*724ba675SRob Herring compatible = "ti,divider-clock"; 216*724ba675SRob Herring clock-output-names = "dpll_core_m5_ck"; 217*724ba675SRob Herring clocks = <&dpll_core_x2_ck>; 218*724ba675SRob Herring ti,max-div = <31>; 219*724ba675SRob Herring reg = <0x0484>; 220*724ba675SRob Herring ti,index-starts-at-one; 221*724ba675SRob Herring }; 222*724ba675SRob Herring 223*724ba675SRob Herring dpll_core_m6_ck: clock-dpll-core-m6@4d8 { 224*724ba675SRob Herring #clock-cells = <0>; 225*724ba675SRob Herring compatible = "ti,divider-clock"; 226*724ba675SRob Herring clock-output-names = "dpll_core_m6_ck"; 227*724ba675SRob Herring clocks = <&dpll_core_x2_ck>; 228*724ba675SRob Herring ti,max-div = <31>; 229*724ba675SRob Herring reg = <0x04d8>; 230*724ba675SRob Herring ti,index-starts-at-one; 231*724ba675SRob Herring }; 232*724ba675SRob Herring 233*724ba675SRob Herring dpll_mpu_ck: clock@488 { 234*724ba675SRob Herring #clock-cells = <0>; 235*724ba675SRob Herring compatible = "ti,am3-dpll-clock"; 236*724ba675SRob Herring clock-output-names = "dpll_mpu_ck"; 237*724ba675SRob Herring clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 238*724ba675SRob Herring reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>; 239*724ba675SRob Herring }; 240*724ba675SRob Herring 241*724ba675SRob Herring dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 { 242*724ba675SRob Herring #clock-cells = <0>; 243*724ba675SRob Herring compatible = "ti,divider-clock"; 244*724ba675SRob Herring clock-output-names = "dpll_mpu_m2_ck"; 245*724ba675SRob Herring clocks = <&dpll_mpu_ck>; 246*724ba675SRob Herring ti,max-div = <31>; 247*724ba675SRob Herring reg = <0x04a8>; 248*724ba675SRob Herring ti,index-starts-at-one; 249*724ba675SRob Herring }; 250*724ba675SRob Herring 251*724ba675SRob Herring dpll_ddr_ck: clock@494 { 252*724ba675SRob Herring #clock-cells = <0>; 253*724ba675SRob Herring compatible = "ti,am3-dpll-no-gate-clock"; 254*724ba675SRob Herring clock-output-names = "dpll_ddr_ck"; 255*724ba675SRob Herring clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 256*724ba675SRob Herring reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>; 257*724ba675SRob Herring }; 258*724ba675SRob Herring 259*724ba675SRob Herring dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 { 260*724ba675SRob Herring #clock-cells = <0>; 261*724ba675SRob Herring compatible = "ti,divider-clock"; 262*724ba675SRob Herring clock-output-names = "dpll_ddr_m2_ck"; 263*724ba675SRob Herring clocks = <&dpll_ddr_ck>; 264*724ba675SRob Herring ti,max-div = <31>; 265*724ba675SRob Herring reg = <0x04a0>; 266*724ba675SRob Herring ti,index-starts-at-one; 267*724ba675SRob Herring }; 268*724ba675SRob Herring 269*724ba675SRob Herring dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 { 270*724ba675SRob Herring #clock-cells = <0>; 271*724ba675SRob Herring compatible = "fixed-factor-clock"; 272*724ba675SRob Herring clock-output-names = "dpll_ddr_m2_div2_ck"; 273*724ba675SRob Herring clocks = <&dpll_ddr_m2_ck>; 274*724ba675SRob Herring clock-mult = <1>; 275*724ba675SRob Herring clock-div = <2>; 276*724ba675SRob Herring }; 277*724ba675SRob Herring 278*724ba675SRob Herring dpll_disp_ck: clock@498 { 279*724ba675SRob Herring #clock-cells = <0>; 280*724ba675SRob Herring compatible = "ti,am3-dpll-no-gate-clock"; 281*724ba675SRob Herring clock-output-names = "dpll_disp_ck"; 282*724ba675SRob Herring clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 283*724ba675SRob Herring reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>; 284*724ba675SRob Herring }; 285*724ba675SRob Herring 286*724ba675SRob Herring dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 { 287*724ba675SRob Herring #clock-cells = <0>; 288*724ba675SRob Herring compatible = "ti,divider-clock"; 289*724ba675SRob Herring clock-output-names = "dpll_disp_m2_ck"; 290*724ba675SRob Herring clocks = <&dpll_disp_ck>; 291*724ba675SRob Herring ti,max-div = <31>; 292*724ba675SRob Herring reg = <0x04a4>; 293*724ba675SRob Herring ti,index-starts-at-one; 294*724ba675SRob Herring ti,set-rate-parent; 295*724ba675SRob Herring }; 296*724ba675SRob Herring 297*724ba675SRob Herring dpll_per_ck: clock@48c { 298*724ba675SRob Herring #clock-cells = <0>; 299*724ba675SRob Herring compatible = "ti,am3-dpll-no-gate-j-type-clock"; 300*724ba675SRob Herring clock-output-names = "dpll_per_ck"; 301*724ba675SRob Herring clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 302*724ba675SRob Herring reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>; 303*724ba675SRob Herring }; 304*724ba675SRob Herring 305*724ba675SRob Herring dpll_per_m2_ck: clock-dpll-per-m2@4ac { 306*724ba675SRob Herring #clock-cells = <0>; 307*724ba675SRob Herring compatible = "ti,divider-clock"; 308*724ba675SRob Herring clock-output-names = "dpll_per_m2_ck"; 309*724ba675SRob Herring clocks = <&dpll_per_ck>; 310*724ba675SRob Herring ti,max-div = <31>; 311*724ba675SRob Herring reg = <0x04ac>; 312*724ba675SRob Herring ti,index-starts-at-one; 313*724ba675SRob Herring }; 314*724ba675SRob Herring 315*724ba675SRob Herring dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm { 316*724ba675SRob Herring #clock-cells = <0>; 317*724ba675SRob Herring compatible = "fixed-factor-clock"; 318*724ba675SRob Herring clock-output-names = "dpll_per_m2_div4_wkupdm_ck"; 319*724ba675SRob Herring clocks = <&dpll_per_m2_ck>; 320*724ba675SRob Herring clock-mult = <1>; 321*724ba675SRob Herring clock-div = <4>; 322*724ba675SRob Herring }; 323*724ba675SRob Herring 324*724ba675SRob Herring dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 { 325*724ba675SRob Herring #clock-cells = <0>; 326*724ba675SRob Herring compatible = "fixed-factor-clock"; 327*724ba675SRob Herring clock-output-names = "dpll_per_m2_div4_ck"; 328*724ba675SRob Herring clocks = <&dpll_per_m2_ck>; 329*724ba675SRob Herring clock-mult = <1>; 330*724ba675SRob Herring clock-div = <4>; 331*724ba675SRob Herring }; 332*724ba675SRob Herring 333*724ba675SRob Herring clk_24mhz: clock-clk-24mhz { 334*724ba675SRob Herring #clock-cells = <0>; 335*724ba675SRob Herring compatible = "fixed-factor-clock"; 336*724ba675SRob Herring clock-output-names = "clk_24mhz"; 337*724ba675SRob Herring clocks = <&dpll_per_m2_ck>; 338*724ba675SRob Herring clock-mult = <1>; 339*724ba675SRob Herring clock-div = <8>; 340*724ba675SRob Herring }; 341*724ba675SRob Herring 342*724ba675SRob Herring clkdiv32k_ck: clock-clkdiv32k { 343*724ba675SRob Herring #clock-cells = <0>; 344*724ba675SRob Herring compatible = "fixed-factor-clock"; 345*724ba675SRob Herring clock-output-names = "clkdiv32k_ck"; 346*724ba675SRob Herring clocks = <&clk_24mhz>; 347*724ba675SRob Herring clock-mult = <1>; 348*724ba675SRob Herring clock-div = <732>; 349*724ba675SRob Herring }; 350*724ba675SRob Herring 351*724ba675SRob Herring l3_gclk: clock-l3-gclk { 352*724ba675SRob Herring #clock-cells = <0>; 353*724ba675SRob Herring compatible = "fixed-factor-clock"; 354*724ba675SRob Herring clock-output-names = "l3_gclk"; 355*724ba675SRob Herring clocks = <&dpll_core_m4_ck>; 356*724ba675SRob Herring clock-mult = <1>; 357*724ba675SRob Herring clock-div = <1>; 358*724ba675SRob Herring }; 359*724ba675SRob Herring 360*724ba675SRob Herring pruss_ocp_gclk: clock-pruss-ocp-gclk@530 { 361*724ba675SRob Herring #clock-cells = <0>; 362*724ba675SRob Herring compatible = "ti,mux-clock"; 363*724ba675SRob Herring clock-output-names = "pruss_ocp_gclk"; 364*724ba675SRob Herring clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; 365*724ba675SRob Herring reg = <0x0530>; 366*724ba675SRob Herring }; 367*724ba675SRob Herring 368*724ba675SRob Herring mmu_fck: clock-mmu-fck-1@914 { 369*724ba675SRob Herring #clock-cells = <0>; 370*724ba675SRob Herring compatible = "ti,gate-clock"; 371*724ba675SRob Herring clock-output-names = "mmu_fck"; 372*724ba675SRob Herring clocks = <&dpll_core_m4_ck>; 373*724ba675SRob Herring ti,bit-shift = <1>; 374*724ba675SRob Herring reg = <0x0914>; 375*724ba675SRob Herring }; 376*724ba675SRob Herring 377*724ba675SRob Herring timer1_fck: clock-timer1-fck@528 { 378*724ba675SRob Herring #clock-cells = <0>; 379*724ba675SRob Herring compatible = "ti,mux-clock"; 380*724ba675SRob Herring clock-output-names = "timer1_fck"; 381*724ba675SRob Herring clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; 382*724ba675SRob Herring reg = <0x0528>; 383*724ba675SRob Herring }; 384*724ba675SRob Herring 385*724ba675SRob Herring timer2_fck: clock-timer2-fck@508 { 386*724ba675SRob Herring #clock-cells = <0>; 387*724ba675SRob Herring compatible = "ti,mux-clock"; 388*724ba675SRob Herring clock-output-names = "timer2_fck"; 389*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 390*724ba675SRob Herring reg = <0x0508>; 391*724ba675SRob Herring }; 392*724ba675SRob Herring 393*724ba675SRob Herring timer3_fck: clock-timer3-fck@50c { 394*724ba675SRob Herring #clock-cells = <0>; 395*724ba675SRob Herring compatible = "ti,mux-clock"; 396*724ba675SRob Herring clock-output-names = "timer3_fck"; 397*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 398*724ba675SRob Herring reg = <0x050c>; 399*724ba675SRob Herring }; 400*724ba675SRob Herring 401*724ba675SRob Herring timer4_fck: clock-timer4-fck@510 { 402*724ba675SRob Herring #clock-cells = <0>; 403*724ba675SRob Herring compatible = "ti,mux-clock"; 404*724ba675SRob Herring clock-output-names = "timer4_fck"; 405*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 406*724ba675SRob Herring reg = <0x0510>; 407*724ba675SRob Herring }; 408*724ba675SRob Herring 409*724ba675SRob Herring timer5_fck: clock-timer5-fck@518 { 410*724ba675SRob Herring #clock-cells = <0>; 411*724ba675SRob Herring compatible = "ti,mux-clock"; 412*724ba675SRob Herring clock-output-names = "timer5_fck"; 413*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 414*724ba675SRob Herring reg = <0x0518>; 415*724ba675SRob Herring }; 416*724ba675SRob Herring 417*724ba675SRob Herring timer6_fck: clock-timer6-fck@51c { 418*724ba675SRob Herring #clock-cells = <0>; 419*724ba675SRob Herring compatible = "ti,mux-clock"; 420*724ba675SRob Herring clock-output-names = "timer6_fck"; 421*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 422*724ba675SRob Herring reg = <0x051c>; 423*724ba675SRob Herring }; 424*724ba675SRob Herring 425*724ba675SRob Herring timer7_fck: clock-timer7-fck@504 { 426*724ba675SRob Herring #clock-cells = <0>; 427*724ba675SRob Herring compatible = "ti,mux-clock"; 428*724ba675SRob Herring clock-output-names = "timer7_fck"; 429*724ba675SRob Herring clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 430*724ba675SRob Herring reg = <0x0504>; 431*724ba675SRob Herring }; 432*724ba675SRob Herring 433*724ba675SRob Herring usbotg_fck: clock-usbotg-fck-8@47c { 434*724ba675SRob Herring #clock-cells = <0>; 435*724ba675SRob Herring compatible = "ti,gate-clock"; 436*724ba675SRob Herring clock-output-names = "usbotg_fck"; 437*724ba675SRob Herring clocks = <&dpll_per_ck>; 438*724ba675SRob Herring ti,bit-shift = <8>; 439*724ba675SRob Herring reg = <0x047c>; 440*724ba675SRob Herring }; 441*724ba675SRob Herring 442*724ba675SRob Herring dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 { 443*724ba675SRob Herring #clock-cells = <0>; 444*724ba675SRob Herring compatible = "fixed-factor-clock"; 445*724ba675SRob Herring clock-output-names = "dpll_core_m4_div2_ck"; 446*724ba675SRob Herring clocks = <&dpll_core_m4_ck>; 447*724ba675SRob Herring clock-mult = <1>; 448*724ba675SRob Herring clock-div = <2>; 449*724ba675SRob Herring }; 450*724ba675SRob Herring 451*724ba675SRob Herring ieee5000_fck: clock-ieee5000-fck-1@e4 { 452*724ba675SRob Herring #clock-cells = <0>; 453*724ba675SRob Herring compatible = "ti,gate-clock"; 454*724ba675SRob Herring clock-output-names = "ieee5000_fck"; 455*724ba675SRob Herring clocks = <&dpll_core_m4_div2_ck>; 456*724ba675SRob Herring ti,bit-shift = <1>; 457*724ba675SRob Herring reg = <0x00e4>; 458*724ba675SRob Herring }; 459*724ba675SRob Herring 460*724ba675SRob Herring wdt1_fck: clock-wdt1-fck@538 { 461*724ba675SRob Herring #clock-cells = <0>; 462*724ba675SRob Herring compatible = "ti,mux-clock"; 463*724ba675SRob Herring clock-output-names = "wdt1_fck"; 464*724ba675SRob Herring clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 465*724ba675SRob Herring reg = <0x0538>; 466*724ba675SRob Herring }; 467*724ba675SRob Herring 468*724ba675SRob Herring l4_rtc_gclk: clock-l4-rtc-gclk { 469*724ba675SRob Herring #clock-cells = <0>; 470*724ba675SRob Herring compatible = "fixed-factor-clock"; 471*724ba675SRob Herring clock-output-names = "l4_rtc_gclk"; 472*724ba675SRob Herring clocks = <&dpll_core_m4_ck>; 473*724ba675SRob Herring clock-mult = <1>; 474*724ba675SRob Herring clock-div = <2>; 475*724ba675SRob Herring }; 476*724ba675SRob Herring 477*724ba675SRob Herring l4hs_gclk: clock-l4hs-gclk { 478*724ba675SRob Herring #clock-cells = <0>; 479*724ba675SRob Herring compatible = "fixed-factor-clock"; 480*724ba675SRob Herring clock-output-names = "l4hs_gclk"; 481*724ba675SRob Herring clocks = <&dpll_core_m4_ck>; 482*724ba675SRob Herring clock-mult = <1>; 483*724ba675SRob Herring clock-div = <1>; 484*724ba675SRob Herring }; 485*724ba675SRob Herring 486*724ba675SRob Herring l3s_gclk: clock-l3s-gclk { 487*724ba675SRob Herring #clock-cells = <0>; 488*724ba675SRob Herring compatible = "fixed-factor-clock"; 489*724ba675SRob Herring clock-output-names = "l3s_gclk"; 490*724ba675SRob Herring clocks = <&dpll_core_m4_div2_ck>; 491*724ba675SRob Herring clock-mult = <1>; 492*724ba675SRob Herring clock-div = <1>; 493*724ba675SRob Herring }; 494*724ba675SRob Herring 495*724ba675SRob Herring l4fw_gclk: clock-l4fw-gclk { 496*724ba675SRob Herring #clock-cells = <0>; 497*724ba675SRob Herring compatible = "fixed-factor-clock"; 498*724ba675SRob Herring clock-output-names = "l4fw_gclk"; 499*724ba675SRob Herring clocks = <&dpll_core_m4_div2_ck>; 500*724ba675SRob Herring clock-mult = <1>; 501*724ba675SRob Herring clock-div = <1>; 502*724ba675SRob Herring }; 503*724ba675SRob Herring 504*724ba675SRob Herring l4ls_gclk: clock-l4ls-gclk { 505*724ba675SRob Herring #clock-cells = <0>; 506*724ba675SRob Herring compatible = "fixed-factor-clock"; 507*724ba675SRob Herring clock-output-names = "l4ls_gclk"; 508*724ba675SRob Herring clocks = <&dpll_core_m4_div2_ck>; 509*724ba675SRob Herring clock-mult = <1>; 510*724ba675SRob Herring clock-div = <1>; 511*724ba675SRob Herring }; 512*724ba675SRob Herring 513*724ba675SRob Herring sysclk_div_ck: clock-sysclk-div { 514*724ba675SRob Herring #clock-cells = <0>; 515*724ba675SRob Herring compatible = "fixed-factor-clock"; 516*724ba675SRob Herring clock-output-names = "sysclk_div_ck"; 517*724ba675SRob Herring clocks = <&dpll_core_m4_ck>; 518*724ba675SRob Herring clock-mult = <1>; 519*724ba675SRob Herring clock-div = <1>; 520*724ba675SRob Herring }; 521*724ba675SRob Herring 522*724ba675SRob Herring cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk { 523*724ba675SRob Herring #clock-cells = <0>; 524*724ba675SRob Herring compatible = "fixed-factor-clock"; 525*724ba675SRob Herring clock-output-names = "cpsw_125mhz_gclk"; 526*724ba675SRob Herring clocks = <&dpll_core_m5_ck>; 527*724ba675SRob Herring clock-mult = <1>; 528*724ba675SRob Herring clock-div = <2>; 529*724ba675SRob Herring }; 530*724ba675SRob Herring 531*724ba675SRob Herring cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 { 532*724ba675SRob Herring #clock-cells = <0>; 533*724ba675SRob Herring compatible = "ti,mux-clock"; 534*724ba675SRob Herring clock-output-names = "cpsw_cpts_rft_clk"; 535*724ba675SRob Herring clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; 536*724ba675SRob Herring reg = <0x0520>; 537*724ba675SRob Herring }; 538*724ba675SRob Herring 539*724ba675SRob Herring gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c { 540*724ba675SRob Herring #clock-cells = <0>; 541*724ba675SRob Herring compatible = "ti,mux-clock"; 542*724ba675SRob Herring clock-output-names = "gpio0_dbclk_mux_ck"; 543*724ba675SRob Herring clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 544*724ba675SRob Herring reg = <0x053c>; 545*724ba675SRob Herring }; 546*724ba675SRob Herring 547*724ba675SRob Herring lcd_gclk: clock-lcd-gclk@534 { 548*724ba675SRob Herring #clock-cells = <0>; 549*724ba675SRob Herring compatible = "ti,mux-clock"; 550*724ba675SRob Herring clock-output-names = "lcd_gclk"; 551*724ba675SRob Herring clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; 552*724ba675SRob Herring reg = <0x0534>; 553*724ba675SRob Herring ti,set-rate-parent; 554*724ba675SRob Herring }; 555*724ba675SRob Herring 556*724ba675SRob Herring mmc_clk: clock-mmc { 557*724ba675SRob Herring #clock-cells = <0>; 558*724ba675SRob Herring compatible = "fixed-factor-clock"; 559*724ba675SRob Herring clock-output-names = "mmc_clk"; 560*724ba675SRob Herring clocks = <&dpll_per_m2_ck>; 561*724ba675SRob Herring clock-mult = <1>; 562*724ba675SRob Herring clock-div = <2>; 563*724ba675SRob Herring }; 564*724ba675SRob Herring 565*724ba675SRob Herring clock@52c { 566*724ba675SRob Herring compatible = "ti,clksel"; 567*724ba675SRob Herring reg = <0x52c>; 568*724ba675SRob Herring #clock-cells = <2>; 569*724ba675SRob Herring #address-cells = <0>; 570*724ba675SRob Herring 571*724ba675SRob Herring gfx_fclk_clksel_ck: clock-gfx-fclk-clksel { 572*724ba675SRob Herring #clock-cells = <0>; 573*724ba675SRob Herring compatible = "ti,mux-clock"; 574*724ba675SRob Herring clock-output-names = "gfx_fclk_clksel_ck"; 575*724ba675SRob Herring clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; 576*724ba675SRob Herring ti,bit-shift = <1>; 577*724ba675SRob Herring }; 578*724ba675SRob Herring 579*724ba675SRob Herring gfx_fck_div_ck: clock-gfx-fck-div { 580*724ba675SRob Herring #clock-cells = <0>; 581*724ba675SRob Herring compatible = "ti,divider-clock"; 582*724ba675SRob Herring clock-output-names = "gfx_fck_div_ck"; 583*724ba675SRob Herring clocks = <&gfx_fclk_clksel_ck>; 584*724ba675SRob Herring ti,max-div = <2>; 585*724ba675SRob Herring }; 586*724ba675SRob Herring }; 587*724ba675SRob Herring 588*724ba675SRob Herring clock@700 { 589*724ba675SRob Herring compatible = "ti,clksel"; 590*724ba675SRob Herring reg = <0x700>; 591*724ba675SRob Herring #clock-cells = <2>; 592*724ba675SRob Herring #address-cells = <0>; 593*724ba675SRob Herring 594*724ba675SRob Herring sysclkout_pre_ck: clock-sysclkout-pre { 595*724ba675SRob Herring #clock-cells = <0>; 596*724ba675SRob Herring compatible = "ti,mux-clock"; 597*724ba675SRob Herring clock-output-names = "sysclkout_pre_ck"; 598*724ba675SRob Herring clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; 599*724ba675SRob Herring }; 600*724ba675SRob Herring 601*724ba675SRob Herring clkout2_div_ck: clock-clkout2-div { 602*724ba675SRob Herring #clock-cells = <0>; 603*724ba675SRob Herring compatible = "ti,divider-clock"; 604*724ba675SRob Herring clock-output-names = "clkout2_div_ck"; 605*724ba675SRob Herring clocks = <&sysclkout_pre_ck>; 606*724ba675SRob Herring ti,bit-shift = <3>; 607*724ba675SRob Herring ti,max-div = <8>; 608*724ba675SRob Herring }; 609*724ba675SRob Herring 610*724ba675SRob Herring clkout2_ck: clock-clkout2 { 611*724ba675SRob Herring #clock-cells = <0>; 612*724ba675SRob Herring compatible = "ti,gate-clock"; 613*724ba675SRob Herring clock-output-names = "clkout2_ck"; 614*724ba675SRob Herring clocks = <&clkout2_div_ck>; 615*724ba675SRob Herring ti,bit-shift = <7>; 616*724ba675SRob Herring }; 617*724ba675SRob Herring }; 618*724ba675SRob Herring}; 619*724ba675SRob Herring 620*724ba675SRob Herring&prcm { 621*724ba675SRob Herring per_cm: clock@0 { 622*724ba675SRob Herring compatible = "ti,omap4-cm"; 623*724ba675SRob Herring clock-output-names = "per_cm"; 624*724ba675SRob Herring reg = <0x0 0x400>; 625*724ba675SRob Herring #address-cells = <1>; 626*724ba675SRob Herring #size-cells = <1>; 627*724ba675SRob Herring ranges = <0 0x0 0x400>; 628*724ba675SRob Herring 629*724ba675SRob Herring l4ls_clkctrl: clock@38 { 630*724ba675SRob Herring compatible = "ti,clkctrl"; 631*724ba675SRob Herring clock-output-names = "l4ls_clkctrl"; 632*724ba675SRob Herring reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>; 633*724ba675SRob Herring #clock-cells = <2>; 634*724ba675SRob Herring }; 635*724ba675SRob Herring 636*724ba675SRob Herring l3s_clkctrl: clock@1c { 637*724ba675SRob Herring compatible = "ti,clkctrl"; 638*724ba675SRob Herring clock-output-names = "l3s_clkctrl"; 639*724ba675SRob Herring reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>; 640*724ba675SRob Herring #clock-cells = <2>; 641*724ba675SRob Herring }; 642*724ba675SRob Herring 643*724ba675SRob Herring l3_clkctrl: clock@24 { 644*724ba675SRob Herring compatible = "ti,clkctrl"; 645*724ba675SRob Herring clock-output-names = "l3_clkctrl"; 646*724ba675SRob Herring reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>; 647*724ba675SRob Herring #clock-cells = <2>; 648*724ba675SRob Herring }; 649*724ba675SRob Herring 650*724ba675SRob Herring l4hs_clkctrl: clock@120 { 651*724ba675SRob Herring compatible = "ti,clkctrl"; 652*724ba675SRob Herring clock-output-names = "l4hs_clkctrl"; 653*724ba675SRob Herring reg = <0x120 0x4>; 654*724ba675SRob Herring #clock-cells = <2>; 655*724ba675SRob Herring }; 656*724ba675SRob Herring 657*724ba675SRob Herring pruss_ocp_clkctrl: clock@e8 { 658*724ba675SRob Herring compatible = "ti,clkctrl"; 659*724ba675SRob Herring clock-output-names = "pruss_ocp_clkctrl"; 660*724ba675SRob Herring reg = <0xe8 0x4>; 661*724ba675SRob Herring #clock-cells = <2>; 662*724ba675SRob Herring }; 663*724ba675SRob Herring 664*724ba675SRob Herring cpsw_125mhz_clkctrl: clock@0 { 665*724ba675SRob Herring compatible = "ti,clkctrl"; 666*724ba675SRob Herring clock-output-names = "cpsw_125mhz_clkctrl"; 667*724ba675SRob Herring reg = <0x0 0x18>; 668*724ba675SRob Herring #clock-cells = <2>; 669*724ba675SRob Herring }; 670*724ba675SRob Herring 671*724ba675SRob Herring lcdc_clkctrl: clock@18 { 672*724ba675SRob Herring compatible = "ti,clkctrl"; 673*724ba675SRob Herring clock-output-names = "lcdc_clkctrl"; 674*724ba675SRob Herring reg = <0x18 0x4>; 675*724ba675SRob Herring #clock-cells = <2>; 676*724ba675SRob Herring }; 677*724ba675SRob Herring 678*724ba675SRob Herring clk_24mhz_clkctrl: clock@14c { 679*724ba675SRob Herring compatible = "ti,clkctrl"; 680*724ba675SRob Herring clock-output-names = "clk_24mhz_clkctrl"; 681*724ba675SRob Herring reg = <0x14c 0x4>; 682*724ba675SRob Herring #clock-cells = <2>; 683*724ba675SRob Herring }; 684*724ba675SRob Herring }; 685*724ba675SRob Herring 686*724ba675SRob Herring wkup_cm: clock@400 { 687*724ba675SRob Herring compatible = "ti,omap4-cm"; 688*724ba675SRob Herring clock-output-names = "wkup_cm"; 689*724ba675SRob Herring reg = <0x400 0x100>; 690*724ba675SRob Herring #address-cells = <1>; 691*724ba675SRob Herring #size-cells = <1>; 692*724ba675SRob Herring ranges = <0 0x400 0x100>; 693*724ba675SRob Herring 694*724ba675SRob Herring l4_wkup_clkctrl: clock@0 { 695*724ba675SRob Herring compatible = "ti,clkctrl"; 696*724ba675SRob Herring clock-output-names = "l4_wkup_clkctrl"; 697*724ba675SRob Herring reg = <0x0 0x10>, <0xb4 0x24>; 698*724ba675SRob Herring #clock-cells = <2>; 699*724ba675SRob Herring }; 700*724ba675SRob Herring 701*724ba675SRob Herring l3_aon_clkctrl: clock@14 { 702*724ba675SRob Herring compatible = "ti,clkctrl"; 703*724ba675SRob Herring clock-output-names = "l3_aon_clkctrl"; 704*724ba675SRob Herring reg = <0x14 0x4>; 705*724ba675SRob Herring #clock-cells = <2>; 706*724ba675SRob Herring }; 707*724ba675SRob Herring 708*724ba675SRob Herring l4_wkup_aon_clkctrl: clock@b0 { 709*724ba675SRob Herring compatible = "ti,clkctrl"; 710*724ba675SRob Herring clock-output-names = "l4_wkup_aon_clkctrl"; 711*724ba675SRob Herring reg = <0xb0 0x4>; 712*724ba675SRob Herring #clock-cells = <2>; 713*724ba675SRob Herring }; 714*724ba675SRob Herring }; 715*724ba675SRob Herring 716*724ba675SRob Herring mpu_cm: clock@600 { 717*724ba675SRob Herring compatible = "ti,omap4-cm"; 718*724ba675SRob Herring clock-output-names = "mpu_cm"; 719*724ba675SRob Herring reg = <0x600 0x100>; 720*724ba675SRob Herring #address-cells = <1>; 721*724ba675SRob Herring #size-cells = <1>; 722*724ba675SRob Herring ranges = <0 0x600 0x100>; 723*724ba675SRob Herring 724*724ba675SRob Herring mpu_clkctrl: clock@0 { 725*724ba675SRob Herring compatible = "ti,clkctrl"; 726*724ba675SRob Herring clock-output-names = "mpu_clkctrl"; 727*724ba675SRob Herring reg = <0x0 0x8>; 728*724ba675SRob Herring #clock-cells = <2>; 729*724ba675SRob Herring }; 730*724ba675SRob Herring }; 731*724ba675SRob Herring 732*724ba675SRob Herring l4_rtc_cm: clock@800 { 733*724ba675SRob Herring compatible = "ti,omap4-cm"; 734*724ba675SRob Herring clock-output-names = "l4_rtc_cm"; 735*724ba675SRob Herring reg = <0x800 0x100>; 736*724ba675SRob Herring #address-cells = <1>; 737*724ba675SRob Herring #size-cells = <1>; 738*724ba675SRob Herring ranges = <0 0x800 0x100>; 739*724ba675SRob Herring 740*724ba675SRob Herring l4_rtc_clkctrl: clock@0 { 741*724ba675SRob Herring compatible = "ti,clkctrl"; 742*724ba675SRob Herring clock-output-names = "l4_rtc_clkctrl"; 743*724ba675SRob Herring reg = <0x0 0x4>; 744*724ba675SRob Herring #clock-cells = <2>; 745*724ba675SRob Herring }; 746*724ba675SRob Herring }; 747*724ba675SRob Herring 748*724ba675SRob Herring gfx_l3_cm: clock@900 { 749*724ba675SRob Herring compatible = "ti,omap4-cm"; 750*724ba675SRob Herring clock-output-names = "gfx_l3_cm"; 751*724ba675SRob Herring reg = <0x900 0x100>; 752*724ba675SRob Herring #address-cells = <1>; 753*724ba675SRob Herring #size-cells = <1>; 754*724ba675SRob Herring ranges = <0 0x900 0x100>; 755*724ba675SRob Herring 756*724ba675SRob Herring gfx_l3_clkctrl: clock@0 { 757*724ba675SRob Herring compatible = "ti,clkctrl"; 758*724ba675SRob Herring clock-output-names = "gfx_l3_clkctrl"; 759*724ba675SRob Herring reg = <0x0 0x8>; 760*724ba675SRob Herring #clock-cells = <2>; 761*724ba675SRob Herring }; 762*724ba675SRob Herring }; 763*724ba675SRob Herring 764*724ba675SRob Herring l4_cefuse_cm: clock@a00 { 765*724ba675SRob Herring compatible = "ti,omap4-cm"; 766*724ba675SRob Herring clock-output-names = "l4_cefuse_cm"; 767*724ba675SRob Herring reg = <0xa00 0x100>; 768*724ba675SRob Herring #address-cells = <1>; 769*724ba675SRob Herring #size-cells = <1>; 770*724ba675SRob Herring ranges = <0 0xa00 0x100>; 771*724ba675SRob Herring 772*724ba675SRob Herring l4_cefuse_clkctrl: clock@0 { 773*724ba675SRob Herring compatible = "ti,clkctrl"; 774*724ba675SRob Herring clock-output-names = "l4_cefuse_clkctrl"; 775*724ba675SRob Herring reg = <0x0 0x24>; 776*724ba675SRob Herring #clock-cells = <2>; 777*724ba675SRob Herring }; 778*724ba675SRob Herring }; 779*724ba675SRob Herring}; 780