1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2819833afSPeter Tyser /* 3819833afSPeter Tyser * (C) Copyright 2006-2008 4819833afSPeter Tyser * Texas Instruments, <www.ti.com> 5819833afSPeter Tyser */ 6819833afSPeter Tyser 7819833afSPeter Tyser #ifndef _CPU_H 8819833afSPeter Tyser #define _CPU_H 9819833afSPeter Tyser 10819833afSPeter Tyser #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 11819833afSPeter Tyser #include <asm/types.h> 12819833afSPeter Tyser #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ 13819833afSPeter Tyser 14819833afSPeter Tyser /* Register offsets of common modules */ 15819833afSPeter Tyser /* Control */ 16819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 17819833afSPeter Tyser #ifndef __ASSEMBLY__ 18819833afSPeter Tyser struct ctrl { 19819833afSPeter Tyser u8 res1[0xC0]; 20819833afSPeter Tyser u16 gpmc_nadv_ale; /* 0xC0 */ 21819833afSPeter Tyser u16 gpmc_noe; /* 0xC2 */ 22819833afSPeter Tyser u16 gpmc_nwe; /* 0xC4 */ 23819833afSPeter Tyser u8 res2[0x22A]; 24819833afSPeter Tyser u32 status; /* 0x2F0 */ 25819833afSPeter Tyser u32 gpstatus; /* 0x2F4 */ 26819833afSPeter Tyser u8 res3[0x08]; 27819833afSPeter Tyser u32 rpubkey_0; /* 0x300 */ 28819833afSPeter Tyser u32 rpubkey_1; /* 0x304 */ 29819833afSPeter Tyser u32 rpubkey_2; /* 0x308 */ 30819833afSPeter Tyser u32 rpubkey_3; /* 0x30C */ 31819833afSPeter Tyser u32 rpubkey_4; /* 0x310 */ 32819833afSPeter Tyser u8 res4[0x04]; 33819833afSPeter Tyser u32 randkey_0; /* 0x318 */ 34819833afSPeter Tyser u32 randkey_1; /* 0x31C */ 35819833afSPeter Tyser u32 randkey_2; /* 0x320 */ 36819833afSPeter Tyser u32 randkey_3; /* 0x324 */ 37819833afSPeter Tyser u8 res5[0x124]; 38819833afSPeter Tyser u32 ctrl_omap_stat; /* 0x44C */ 39819833afSPeter Tyser }; 40819833afSPeter Tyser #else /* __ASSEMBLY__ */ 41819833afSPeter Tyser #define CONTROL_STATUS 0x2F0 42819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 43819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 44819833afSPeter Tyser 45819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 46819833afSPeter Tyser #ifndef __ASSEMBLY__ 47819833afSPeter Tyser struct ctrl_id { 48819833afSPeter Tyser u8 res1[0x4]; 49819833afSPeter Tyser u32 idcode; /* 0x04 */ 50819833afSPeter Tyser u32 prod_id; /* 0x08 */ 51b2b9169fSSteve Sakoman u32 sku_id; /* 0x0c */ 52b2b9169fSSteve Sakoman u8 res2[0x08]; 53819833afSPeter Tyser u32 die_id_0; /* 0x18 */ 54819833afSPeter Tyser u32 die_id_1; /* 0x1C */ 55819833afSPeter Tyser u32 die_id_2; /* 0x20 */ 56819833afSPeter Tyser u32 die_id_3; /* 0x24 */ 57819833afSPeter Tyser }; 58819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 59819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 60819833afSPeter Tyser 6147c331edSDaniel Allred /* boot pin mask */ 62819833afSPeter Tyser #define SYSBOOT_MASK 0x1F 63819833afSPeter Tyser 64b2b9169fSSteve Sakoman /* device speed */ 65b2b9169fSSteve Sakoman #define SKUID_CLK_MASK 0xf 66b2b9169fSSteve Sakoman #define SKUID_CLK_600MHZ 0x0 67b2b9169fSSteve Sakoman #define SKUID_CLK_720MHZ 0x8 68b2b9169fSSteve Sakoman 69819833afSPeter Tyser #define GPMC_BASE (OMAP34XX_GPMC_BASE) 70819833afSPeter Tyser #define GPMC_CONFIG_CS0 0x60 71819833afSPeter Tyser #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) 72819833afSPeter Tyser 73819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 7451d192c4Spekon gupta #ifdef __ASSEMBLY__ 75819833afSPeter Tyser #define GPMC_CONFIG1 0x00 76819833afSPeter Tyser #define GPMC_CONFIG2 0x04 77819833afSPeter Tyser #define GPMC_CONFIG3 0x08 78819833afSPeter Tyser #define GPMC_CONFIG4 0x0C 79819833afSPeter Tyser #define GPMC_CONFIG5 0x10 80819833afSPeter Tyser #define GPMC_CONFIG6 0x14 81819833afSPeter Tyser #define GPMC_CONFIG7 0x18 82819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 83819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 84819833afSPeter Tyser 85819833afSPeter Tyser /* GPMC Mapping */ 86819833afSPeter Tyser #define FLASH_BASE 0x10000000 /* NOR flash, */ 87819833afSPeter Tyser /* aligned to 256 Meg */ 88819833afSPeter Tyser #define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */ 89819833afSPeter Tyser /* aligned to 64 Meg */ 90819833afSPeter Tyser #define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */ 91819833afSPeter Tyser /* aligned to 256 Meg */ 92819833afSPeter Tyser #define DEBUG_BASE 0x08000000 /* debug board */ 93819833afSPeter Tyser #define NAND_BASE 0x30000000 /* NAND addr */ 94819833afSPeter Tyser /* (actual size small port) */ 95819833afSPeter Tyser #define ONENAND_MAP 0x20000000 /* OneNand addr */ 96819833afSPeter Tyser /* (actual size small port) */ 97819833afSPeter Tyser /* SMS */ 98819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 99819833afSPeter Tyser #ifndef __ASSEMBLY__ 100819833afSPeter Tyser struct sms { 101819833afSPeter Tyser u8 res1[0x10]; 102819833afSPeter Tyser u32 sysconfig; /* 0x10 */ 103819833afSPeter Tyser u8 res2[0x34]; 104819833afSPeter Tyser u32 rg_att0; /* 0x48 */ 105819833afSPeter Tyser u8 res3[0x84]; 106819833afSPeter Tyser u32 class_arb0; /* 0xD0 */ 107819833afSPeter Tyser }; 108819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 109819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 110819833afSPeter Tyser 111819833afSPeter Tyser #define BURSTCOMPLETE_GROUP7 (0x1 << 31) 112819833afSPeter Tyser 113819833afSPeter Tyser /* SDRC */ 114819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 115819833afSPeter Tyser #ifndef __ASSEMBLY__ 116819833afSPeter Tyser struct sdrc_cs { 117819833afSPeter Tyser u32 mcfg; /* 0x80 || 0xB0 */ 118819833afSPeter Tyser u32 mr; /* 0x84 || 0xB4 */ 119819833afSPeter Tyser u8 res1[0x4]; 120819833afSPeter Tyser u32 emr2; /* 0x8C || 0xBC */ 121819833afSPeter Tyser u8 res2[0x14]; 122819833afSPeter Tyser u32 rfr_ctrl; /* 0x84 || 0xD4 */ 123819833afSPeter Tyser u32 manual; /* 0xA8 || 0xD8 */ 124819833afSPeter Tyser u8 res3[0x4]; 125819833afSPeter Tyser }; 126819833afSPeter Tyser 127819833afSPeter Tyser struct sdrc_actim { 128819833afSPeter Tyser u32 ctrla; /* 0x9C || 0xC4 */ 129819833afSPeter Tyser u32 ctrlb; /* 0xA0 || 0xC8 */ 130819833afSPeter Tyser }; 131819833afSPeter Tyser 132819833afSPeter Tyser struct sdrc { 133819833afSPeter Tyser u8 res1[0x10]; 134819833afSPeter Tyser u32 sysconfig; /* 0x10 */ 135819833afSPeter Tyser u32 status; /* 0x14 */ 136819833afSPeter Tyser u8 res2[0x28]; 137819833afSPeter Tyser u32 cs_cfg; /* 0x40 */ 138819833afSPeter Tyser u32 sharing; /* 0x44 */ 139819833afSPeter Tyser u8 res3[0x18]; 140819833afSPeter Tyser u32 dlla_ctrl; /* 0x60 */ 141819833afSPeter Tyser u32 dlla_status; /* 0x64 */ 142819833afSPeter Tyser u32 dllb_ctrl; /* 0x68 */ 143819833afSPeter Tyser u32 dllb_status; /* 0x6C */ 144819833afSPeter Tyser u32 power; /* 0x70 */ 145819833afSPeter Tyser u8 res4[0xC]; 146819833afSPeter Tyser struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */ 147819833afSPeter Tyser }; 148cae377b5SVaibhav Hiremath 1491a5038caSVaibhav Hiremath /* EMIF4 */ 1501a5038caSVaibhav Hiremath typedef struct emif4 { 15140b95c89SIlya Yanok unsigned int emif_mod_id_rev; 1521a5038caSVaibhav Hiremath unsigned int sdram_sts; 1531a5038caSVaibhav Hiremath unsigned int sdram_config; 1541a5038caSVaibhav Hiremath unsigned int res1; 1551a5038caSVaibhav Hiremath unsigned int sdram_refresh_ctrl; 1561a5038caSVaibhav Hiremath unsigned int sdram_refresh_ctrl_shdw; 1571a5038caSVaibhav Hiremath unsigned int sdram_time1; 1581a5038caSVaibhav Hiremath unsigned int sdram_time1_shdw; 1591a5038caSVaibhav Hiremath unsigned int sdram_time2; 1601a5038caSVaibhav Hiremath unsigned int sdram_time2_shdw; 1611a5038caSVaibhav Hiremath unsigned int sdram_time3; 1621a5038caSVaibhav Hiremath unsigned int sdram_time3_shdw; 1631a5038caSVaibhav Hiremath unsigned char res2[8]; 1641a5038caSVaibhav Hiremath unsigned int sdram_pwr_mgmt; 1651a5038caSVaibhav Hiremath unsigned int sdram_pwr_mgmt_shdw; 1661a5038caSVaibhav Hiremath unsigned char res3[32]; 1671a5038caSVaibhav Hiremath unsigned int sdram_iodft_tlgc; 1681a5038caSVaibhav Hiremath unsigned char res4[128]; 1691a5038caSVaibhav Hiremath unsigned int ddr_phyctrl1; 1701a5038caSVaibhav Hiremath unsigned int ddr_phyctrl1_shdw; 1711a5038caSVaibhav Hiremath unsigned int ddr_phyctrl2; 1721a5038caSVaibhav Hiremath } emif4_t; 1731a5038caSVaibhav Hiremath 174819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 175819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 176819833afSPeter Tyser 177819833afSPeter Tyser #define DLLPHASE_90 (0x1 << 1) 178819833afSPeter Tyser #define LOADDLL (0x1 << 2) 179819833afSPeter Tyser #define ENADLL (0x1 << 3) 180819833afSPeter Tyser #define DLL_DELAY_MASK 0xFF00 181819833afSPeter Tyser #define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8)) 182819833afSPeter Tyser 183819833afSPeter Tyser #define PAGEPOLICY_HIGH (0x1 << 0) 184819833afSPeter Tyser #define SRFRONRESET (0x1 << 7) 185819833afSPeter Tyser #define PWDNEN (0x1 << 2) 186819833afSPeter Tyser #define WAKEUPPROC (0x1 << 26) 187819833afSPeter Tyser 188819833afSPeter Tyser #define DDR_SDRAM (0x1 << 0) 189819833afSPeter Tyser #define DEEPPD (0x1 << 3) 190819833afSPeter Tyser #define B32NOT16 (0x1 << 4) 191819833afSPeter Tyser #define BANKALLOCATION (0x2 << 6) 192819833afSPeter Tyser #define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */ 193819833afSPeter Tyser #define ADDRMUXLEGACY (0x1 << 19) 194819833afSPeter Tyser #define CASWIDTH_10BITS (0x5 << 20) 195819833afSPeter Tyser #define RASWIDTH_13BITS (0x2 << 24) 196819833afSPeter Tyser #define BURSTLENGTH4 (0x2 << 0) 197819833afSPeter Tyser #define CASL3 (0x3 << 4) 198819833afSPeter Tyser #define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C) 199819833afSPeter Tyser #define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4) 200819833afSPeter Tyser #define ARE_ARCV_1 (0x1 << 0) 201819833afSPeter Tyser #define ARCV (0x4e2 << 8) /* Autorefresh count */ 202819833afSPeter Tyser #define OMAP34XX_SDRC_CS0 0x80000000 203819833afSPeter Tyser #define OMAP34XX_SDRC_CS1 0xA0000000 204819833afSPeter Tyser #define CMD_NOP 0x0 205819833afSPeter Tyser #define CMD_PRECHARGE 0x1 206819833afSPeter Tyser #define CMD_AUTOREFRESH 0x2 207819833afSPeter Tyser #define CMD_ENTR_PWRDOWN 0x3 208819833afSPeter Tyser #define CMD_EXIT_PWRDOWN 0x4 209819833afSPeter Tyser #define CMD_ENTR_SRFRSH 0x5 210819833afSPeter Tyser #define CMD_CKE_HIGH 0x6 211819833afSPeter Tyser #define CMD_CKE_LOW 0x7 212819833afSPeter Tyser #define SOFTRESET (0x1 << 1) 213819833afSPeter Tyser #define SMART_IDLE (0x2 << 3) 214819833afSPeter Tyser #define REF_ON_IDLE (0x1 << 6) 215819833afSPeter Tyser 2167b646a6dSSimon Schwarz /* DMA */ 2177b646a6dSSimon Schwarz #ifndef __KERNEL_STRICT_NAMES 2187b646a6dSSimon Schwarz #ifndef __ASSEMBLY__ 2197b646a6dSSimon Schwarz struct dma4_chan { 2207b646a6dSSimon Schwarz u32 ccr; 2217b646a6dSSimon Schwarz u32 clnk_ctrl; 2227b646a6dSSimon Schwarz u32 cicr; 2237b646a6dSSimon Schwarz u32 csr; 2247b646a6dSSimon Schwarz u32 csdp; 2257b646a6dSSimon Schwarz u32 cen; 2267b646a6dSSimon Schwarz u32 cfn; 2277b646a6dSSimon Schwarz u32 cssa; 2287b646a6dSSimon Schwarz u32 cdsa; 2297b646a6dSSimon Schwarz u32 csel; 2307b646a6dSSimon Schwarz u32 csfl; 2317b646a6dSSimon Schwarz u32 cdel; 2327b646a6dSSimon Schwarz u32 cdfl; 2337b646a6dSSimon Schwarz u32 csac; 2347b646a6dSSimon Schwarz u32 cdac; 2357b646a6dSSimon Schwarz u32 ccen; 2367b646a6dSSimon Schwarz u32 ccfn; 2377b646a6dSSimon Schwarz u32 color; 2387b646a6dSSimon Schwarz }; 2397b646a6dSSimon Schwarz 2407b646a6dSSimon Schwarz struct dma4 { 2417b646a6dSSimon Schwarz u32 revision; 2427b646a6dSSimon Schwarz u8 res1[0x4]; 2437b646a6dSSimon Schwarz u32 irqstatus_l[0x4]; 2447b646a6dSSimon Schwarz u32 irqenable_l[0x4]; 2457b646a6dSSimon Schwarz u32 sysstatus; 2467b646a6dSSimon Schwarz u32 ocp_sysconfig; 2477b646a6dSSimon Schwarz u8 res2[0x34]; 2487b646a6dSSimon Schwarz u32 caps_0; 2497b646a6dSSimon Schwarz u8 res3[0x4]; 2507b646a6dSSimon Schwarz u32 caps_2; 2517b646a6dSSimon Schwarz u32 caps_3; 2527b646a6dSSimon Schwarz u32 caps_4; 2537b646a6dSSimon Schwarz u32 gcr; 2547b646a6dSSimon Schwarz u8 res4[0x4]; 2557b646a6dSSimon Schwarz struct dma4_chan chan[32]; 2567b646a6dSSimon Schwarz }; 2577b646a6dSSimon Schwarz 2587b646a6dSSimon Schwarz #endif /*__ASSEMBLY__ */ 2597b646a6dSSimon Schwarz #endif /* __KERNEL_STRICT_NAMES */ 2607b646a6dSSimon Schwarz 261819833afSPeter Tyser /* timer regs offsets (32 bit regs) */ 262819833afSPeter Tyser 263819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 264819833afSPeter Tyser #ifndef __ASSEMBLY__ 265819833afSPeter Tyser struct gptimer { 266819833afSPeter Tyser u32 tidr; /* 0x00 r */ 267819833afSPeter Tyser u8 res[0xc]; 268819833afSPeter Tyser u32 tiocp_cfg; /* 0x10 rw */ 269819833afSPeter Tyser u32 tistat; /* 0x14 r */ 270819833afSPeter Tyser u32 tisr; /* 0x18 rw */ 271819833afSPeter Tyser u32 tier; /* 0x1c rw */ 272819833afSPeter Tyser u32 twer; /* 0x20 rw */ 273819833afSPeter Tyser u32 tclr; /* 0x24 rw */ 274819833afSPeter Tyser u32 tcrr; /* 0x28 rw */ 275819833afSPeter Tyser u32 tldr; /* 0x2c rw */ 276819833afSPeter Tyser u32 ttgr; /* 0x30 rw */ 277819833afSPeter Tyser u32 twpc; /* 0x34 r*/ 278819833afSPeter Tyser u32 tmar; /* 0x38 rw*/ 279819833afSPeter Tyser u32 tcar1; /* 0x3c r */ 280819833afSPeter Tyser u32 tcicr; /* 0x40 rw */ 281819833afSPeter Tyser u32 tcar2; /* 0x44 r */ 282819833afSPeter Tyser }; 283819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 284819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 285819833afSPeter Tyser 286819833afSPeter Tyser /* enable sys_clk NO-prescale /1 */ 287819833afSPeter Tyser #define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) 288819833afSPeter Tyser 289819833afSPeter Tyser /* Watchdog */ 290819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 291819833afSPeter Tyser #ifndef __ASSEMBLY__ 292819833afSPeter Tyser struct watchdog { 293819833afSPeter Tyser u8 res1[0x34]; 294819833afSPeter Tyser u32 wwps; /* 0x34 r */ 295819833afSPeter Tyser u8 res2[0x10]; 296819833afSPeter Tyser u32 wspr; /* 0x48 rw */ 297819833afSPeter Tyser }; 298819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 299819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 300819833afSPeter Tyser 301819833afSPeter Tyser #define WD_UNLOCK1 0xAAAA 302819833afSPeter Tyser #define WD_UNLOCK2 0x5555 303819833afSPeter Tyser 304819833afSPeter Tyser /* PRCM */ 305819833afSPeter Tyser #define PRCM_BASE 0x48004000 306819833afSPeter Tyser 307819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 308819833afSPeter Tyser #ifndef __ASSEMBLY__ 309819833afSPeter Tyser struct prcm { 310819833afSPeter Tyser u32 fclken_iva2; /* 0x00 */ 311819833afSPeter Tyser u32 clken_pll_iva2; /* 0x04 */ 312819833afSPeter Tyser u8 res1[0x1c]; 313819833afSPeter Tyser u32 idlest_pll_iva2; /* 0x24 */ 314819833afSPeter Tyser u8 res2[0x18]; 315819833afSPeter Tyser u32 clksel1_pll_iva2 ; /* 0x40 */ 316819833afSPeter Tyser u32 clksel2_pll_iva2; /* 0x44 */ 317819833afSPeter Tyser u8 res3[0x8bc]; 318819833afSPeter Tyser u32 clken_pll_mpu; /* 0x904 */ 319819833afSPeter Tyser u8 res4[0x1c]; 320819833afSPeter Tyser u32 idlest_pll_mpu; /* 0x924 */ 321819833afSPeter Tyser u8 res5[0x18]; 322819833afSPeter Tyser u32 clksel1_pll_mpu; /* 0x940 */ 323819833afSPeter Tyser u32 clksel2_pll_mpu; /* 0x944 */ 324819833afSPeter Tyser u8 res6[0xb8]; 325819833afSPeter Tyser u32 fclken1_core; /* 0xa00 */ 3267b89795fSAlexander Holler u32 res_fclken2_core; 3277b89795fSAlexander Holler u32 fclken3_core; /* 0xa08 */ 3287b89795fSAlexander Holler u8 res7[0x4]; 329819833afSPeter Tyser u32 iclken1_core; /* 0xa10 */ 330819833afSPeter Tyser u32 iclken2_core; /* 0xa14 */ 3317b89795fSAlexander Holler u32 iclken3_core; /* 0xa18 */ 3327b89795fSAlexander Holler u8 res8[0x24]; 333819833afSPeter Tyser u32 clksel_core; /* 0xa40 */ 334819833afSPeter Tyser u8 res9[0xbc]; 335819833afSPeter Tyser u32 fclken_gfx; /* 0xb00 */ 336819833afSPeter Tyser u8 res10[0xc]; 337819833afSPeter Tyser u32 iclken_gfx; /* 0xb10 */ 338819833afSPeter Tyser u8 res11[0x2c]; 339819833afSPeter Tyser u32 clksel_gfx; /* 0xb40 */ 340819833afSPeter Tyser u8 res12[0xbc]; 341819833afSPeter Tyser u32 fclken_wkup; /* 0xc00 */ 342819833afSPeter Tyser u8 res13[0xc]; 343819833afSPeter Tyser u32 iclken_wkup; /* 0xc10 */ 344819833afSPeter Tyser u8 res14[0xc]; 345819833afSPeter Tyser u32 idlest_wkup; /* 0xc20 */ 346819833afSPeter Tyser u8 res15[0x1c]; 347819833afSPeter Tyser u32 clksel_wkup; /* 0xc40 */ 348819833afSPeter Tyser u8 res16[0xbc]; 349819833afSPeter Tyser u32 clken_pll; /* 0xd00 */ 3507b89795fSAlexander Holler u32 clken2_pll; /* 0xd04 */ 3517b89795fSAlexander Holler u8 res17[0x18]; 352819833afSPeter Tyser u32 idlest_ckgen; /* 0xd20 */ 3537b89795fSAlexander Holler u32 idlest2_ckgen; /* 0xd24 */ 3547b89795fSAlexander Holler u8 res18[0x18]; 355819833afSPeter Tyser u32 clksel1_pll; /* 0xd40 */ 356819833afSPeter Tyser u32 clksel2_pll; /* 0xd44 */ 357819833afSPeter Tyser u32 clksel3_pll; /* 0xd48 */ 3587b89795fSAlexander Holler u32 clksel4_pll; /* 0xd4c */ 3597b89795fSAlexander Holler u32 clksel5_pll; /* 0xd50 */ 3607b89795fSAlexander Holler u8 res19[0xac]; 361819833afSPeter Tyser u32 fclken_dss; /* 0xe00 */ 362819833afSPeter Tyser u8 res20[0xc]; 363819833afSPeter Tyser u32 iclken_dss; /* 0xe10 */ 364819833afSPeter Tyser u8 res21[0x2c]; 365819833afSPeter Tyser u32 clksel_dss; /* 0xe40 */ 366819833afSPeter Tyser u8 res22[0xbc]; 367819833afSPeter Tyser u32 fclken_cam; /* 0xf00 */ 368819833afSPeter Tyser u8 res23[0xc]; 369819833afSPeter Tyser u32 iclken_cam; /* 0xf10 */ 370819833afSPeter Tyser u8 res24[0x2c]; 371819833afSPeter Tyser u32 clksel_cam; /* 0xf40 */ 372819833afSPeter Tyser u8 res25[0xbc]; 373819833afSPeter Tyser u32 fclken_per; /* 0x1000 */ 374819833afSPeter Tyser u8 res26[0xc]; 375819833afSPeter Tyser u32 iclken_per; /* 0x1010 */ 376819833afSPeter Tyser u8 res27[0x2c]; 377819833afSPeter Tyser u32 clksel_per; /* 0x1040 */ 378819833afSPeter Tyser u8 res28[0xfc]; 379819833afSPeter Tyser u32 clksel1_emu; /* 0x1140 */ 3807b89795fSAlexander Holler u8 res29[0x2bc]; 3817b89795fSAlexander Holler u32 fclken_usbhost; /* 0x1400 */ 3827b89795fSAlexander Holler u8 res30[0xc]; 3837b89795fSAlexander Holler u32 iclken_usbhost; /* 0x1410 */ 384819833afSPeter Tyser }; 385819833afSPeter Tyser #else /* __ASSEMBLY__ */ 386819833afSPeter Tyser #define CM_CLKSEL_CORE 0x48004a40 387819833afSPeter Tyser #define CM_CLKSEL_GFX 0x48004b40 388819833afSPeter Tyser #define CM_CLKSEL_WKUP 0x48004c40 389819833afSPeter Tyser #define CM_CLKEN_PLL 0x48004d00 390819833afSPeter Tyser #define CM_CLKSEL1_PLL 0x48004d40 391819833afSPeter Tyser #define CM_CLKSEL1_EMU 0x48005140 392819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 393819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 394819833afSPeter Tyser 395819833afSPeter Tyser #define PRM_BASE 0x48306000 396819833afSPeter Tyser 397819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 398819833afSPeter Tyser #ifndef __ASSEMBLY__ 399819833afSPeter Tyser struct prm { 400819833afSPeter Tyser u8 res1[0xd40]; 401819833afSPeter Tyser u32 clksel; /* 0xd40 */ 402819833afSPeter Tyser u8 res2[0x50c]; 403819833afSPeter Tyser u32 rstctrl; /* 0x1250 */ 404819833afSPeter Tyser u8 res3[0x1c]; 405819833afSPeter Tyser u32 clksrc_ctrl; /* 0x1270 */ 406819833afSPeter Tyser }; 407819833afSPeter Tyser #endif /* __ASSEMBLY__ */ 408819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 409819833afSPeter Tyser 410d417d1dbSSRICHARAN R #define PRM_RSTCTRL 0x48307250 411d417d1dbSSRICHARAN R #define PRM_RSTCTRL_RESET 0x04 41270239507SLokesh Vutla #define PRM_RSTST 0x48307258 41370239507SLokesh Vutla #define PRM_RSTST_WARM_RESET_MASK 0x7D2 414819833afSPeter Tyser #define SYSCLKDIV_1 (0x1 << 6) 415819833afSPeter Tyser #define SYSCLKDIV_2 (0x1 << 7) 416819833afSPeter Tyser 417819833afSPeter Tyser #define CLKSEL_GPT1 (0x1 << 0) 418819833afSPeter Tyser 419819833afSPeter Tyser #define EN_GPT1 (0x1 << 0) 420819833afSPeter Tyser #define EN_32KSYNC (0x1 << 2) 421819833afSPeter Tyser 422819833afSPeter Tyser #define ST_WDT2 (0x1 << 5) 423819833afSPeter Tyser 424819833afSPeter Tyser #define ST_MPU_CLK (0x1 << 0) 425819833afSPeter Tyser 426819833afSPeter Tyser #define ST_CORE_CLK (0x1 << 0) 427819833afSPeter Tyser 428819833afSPeter Tyser #define ST_PERIPH_CLK (0x1 << 1) 429819833afSPeter Tyser 430819833afSPeter Tyser #define ST_IVA2_CLK (0x1 << 0) 431819833afSPeter Tyser 432819833afSPeter Tyser #define RESETDONE (0x1 << 0) 433819833afSPeter Tyser 434819833afSPeter Tyser #define TCLR_ST (0x1 << 0) 435819833afSPeter Tyser #define TCLR_AR (0x1 << 1) 436819833afSPeter Tyser #define TCLR_PRE (0x1 << 5) 437819833afSPeter Tyser 438819833afSPeter Tyser /* SMX-APE */ 439819833afSPeter Tyser #define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) 440819833afSPeter Tyser #define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) 441819833afSPeter Tyser #define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) 442819833afSPeter Tyser #define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) 443819833afSPeter Tyser 444819833afSPeter Tyser #ifndef __KERNEL_STRICT_NAMES 445819833afSPeter Tyser #ifndef __ASSEMBLY__ 446819833afSPeter Tyser struct pm { 447819833afSPeter Tyser u8 res1[0x48]; 448819833afSPeter Tyser u32 req_info_permission_0; /* 0x48 */ 449819833afSPeter Tyser u8 res2[0x4]; 450819833afSPeter Tyser u32 read_permission_0; /* 0x50 */ 451819833afSPeter Tyser u8 res3[0x4]; 452819833afSPeter Tyser u32 wirte_permission_0; /* 0x58 */ 453819833afSPeter Tyser u8 res4[0x4]; 454819833afSPeter Tyser u32 addr_match_1; /* 0x58 */ 455819833afSPeter Tyser u8 res5[0x4]; 456819833afSPeter Tyser u32 req_info_permission_1; /* 0x68 */ 457819833afSPeter Tyser u8 res6[0x14]; 458819833afSPeter Tyser u32 addr_match_2; /* 0x80 */ 459819833afSPeter Tyser }; 460819833afSPeter Tyser #endif /*__ASSEMBLY__ */ 461819833afSPeter Tyser #endif /* __KERNEL_STRICT_NAMES */ 462819833afSPeter Tyser 463819833afSPeter Tyser /* Permission values for registers -Full fledged permissions to all */ 464819833afSPeter Tyser #define UNLOCK_1 0xFFFFFFFF 465819833afSPeter Tyser #define UNLOCK_2 0x00000000 466819833afSPeter Tyser #define UNLOCK_3 0x0000FFFF 467819833afSPeter Tyser 468819833afSPeter Tyser #define NOT_EARLY 0 469819833afSPeter Tyser 470819833afSPeter Tyser /* I2C base */ 471819833afSPeter Tyser #define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) 472819833afSPeter Tyser #define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) 473819833afSPeter Tyser #define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) 474819833afSPeter Tyser 4759b167577SSteve Sakoman /* MUSB base */ 4769b167577SSteve Sakoman #define MUSB_BASE (OMAP34XX_CORE_L4_IO_BASE + 0xAB000) 4779b167577SSteve Sakoman 47825223a68SAneesh V /* OMAP3 GPIO registers */ 47925223a68SAneesh V #define OMAP_GPIO_REVISION 0x0000 48025223a68SAneesh V #define OMAP_GPIO_SYSCONFIG 0x0010 48125223a68SAneesh V #define OMAP_GPIO_SYSSTATUS 0x0014 48225223a68SAneesh V #define OMAP_GPIO_IRQSTATUS1 0x0018 48325223a68SAneesh V #define OMAP_GPIO_IRQSTATUS2 0x0028 48425223a68SAneesh V #define OMAP_GPIO_IRQENABLE2 0x002c 48525223a68SAneesh V #define OMAP_GPIO_IRQENABLE1 0x001c 48625223a68SAneesh V #define OMAP_GPIO_WAKE_EN 0x0020 48725223a68SAneesh V #define OMAP_GPIO_CTRL 0x0030 48825223a68SAneesh V #define OMAP_GPIO_OE 0x0034 48925223a68SAneesh V #define OMAP_GPIO_DATAIN 0x0038 49025223a68SAneesh V #define OMAP_GPIO_DATAOUT 0x003c 49125223a68SAneesh V #define OMAP_GPIO_LEVELDETECT0 0x0040 49225223a68SAneesh V #define OMAP_GPIO_LEVELDETECT1 0x0044 49325223a68SAneesh V #define OMAP_GPIO_RISINGDETECT 0x0048 49425223a68SAneesh V #define OMAP_GPIO_FALLINGDETECT 0x004c 49525223a68SAneesh V #define OMAP_GPIO_DEBOUNCE_EN 0x0050 49625223a68SAneesh V #define OMAP_GPIO_DEBOUNCE_VAL 0x0054 49725223a68SAneesh V #define OMAP_GPIO_CLEARIRQENABLE1 0x0060 49825223a68SAneesh V #define OMAP_GPIO_SETIRQENABLE1 0x0064 49925223a68SAneesh V #define OMAP_GPIO_CLEARWKUENA 0x0080 50025223a68SAneesh V #define OMAP_GPIO_SETWKUENA 0x0084 50125223a68SAneesh V #define OMAP_GPIO_CLEARDATAOUT 0x0090 50225223a68SAneesh V #define OMAP_GPIO_SETDATAOUT 0x0094 50325223a68SAneesh V 504819833afSPeter Tyser #endif /* _CPU_H */ 505