| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.c | 255 .clk_table = {
404 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn315_build_watermark_ranges()
407 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn315_build_watermark_ranges()
487 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn315_clk_mgr_helper_populate_bw_params()
503 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--) in dcn315_clk_mgr_helper_populate_bw_params()
504 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn315_clk_mgr_helper_populate_bw_params()
506 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
507 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
508 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn315_clk_mgr_helper_populate_bw_params()
511 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[max_pstate].FClk; in dcn315_clk_mgr_helper_populate_bw_params()
[all …]
|
| /openbmc/linux/drivers/clk/samsung/ |
| H A D | clk-s5pv210-audss.c | 69 struct clk_hw **clk_table; in s5pv210_audss_clk_probe() local
84 clk_table = clk_data->hws; in s5pv210_audss_clk_probe()
113 clk_table[CLK_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", in s5pv210_audss_clk_probe()
124 clk_table[CLK_MOUT_I2S_A] = clk_hw_register_mux(NULL, "mout_i2s_audss", in s5pv210_audss_clk_probe()
129 clk_table[CLK_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
132 clk_table[CLK_DOUT_I2S_A] = clk_hw_register_divider(NULL, in s5pv210_audss_clk_probe()
136 clk_table[CLK_I2S] = clk_hw_register_gate(NULL, "i2s_audss", in s5pv210_audss_clk_probe()
142 clk_table[CLK_HCLK_I2S] = clk_hw_register_gate(NULL, "hclk_i2s_audss", in s5pv210_audss_clk_probe()
145 clk_table[CLK_HCLK_UART] = clk_hw_register_gate(NULL, "hclk_uart_audss", in s5pv210_audss_clk_probe()
148 clk_table[CLK_HCLK_HWA] = clk_hw_register_gate(NULL, "hclk_hwa_audss", in s5pv210_audss_clk_probe()
[all …]
|
| H A D | clk-exynos-audss.c | 130 struct clk_hw **clk_table; in exynos_audss_clk_probe() local
152 clk_table = clk_data->hws; in exynos_audss_clk_probe()
183 clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss", in exynos_audss_clk_probe()
194 clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s", in exynos_audss_clk_probe()
199 clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp", in exynos_audss_clk_probe()
203 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev, in exynos_audss_clk_probe()
207 clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s", in exynos_audss_clk_probe()
211 clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk", in exynos_audss_clk_probe()
215 clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus", in exynos_audss_clk_probe()
219 clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s", in exynos_audss_clk_probe()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 585 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn31_update_bw_bounding_box() local
599 ASSERT(clk_table->num_entries); in dcn31_update_bw_bounding_box()
602 for (i = 0; i < clk_table->num_entries; ++i) { in dcn31_update_bw_bounding_box()
603 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn31_update_bw_bounding_box()
604 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn31_update_bw_bounding_box()
605 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn31_update_bw_bounding_box()
606 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn31_update_bw_bounding_box()
609 for (i = 0; i < clk_table->num_entries; i++) { in dcn31_update_bw_bounding_box()
612 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box()
621 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn31_update_bw_bounding_box()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 352 .clk_table = {
459 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn314_build_watermark_ranges()
462 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn314_build_watermark_ranges()
572 …struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entri… in dcn314_clk_mgr_helper_populate_bw_params()
613 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--) in dcn314_clk_mgr_helper_populate_bw_params()
614 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i]) in dcn314_clk_mgr_helper_populate_bw_params()
617 bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
618 bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
619 bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz; in dcn314_clk_mgr_helper_populate_bw_params()
622 bw_params->clk_table.entries[i].fclk_mhz = min_fclk; in dcn314_clk_mgr_helper_populate_bw_params()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/ |
| H A D | dcn321_fpu.c | 365 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_clk_data.dcfclk_mhz) in build_synthetic_soc_states()
366 max_clk_data.dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_synthetic_soc_states()
367 if (bw_params->clk_table.entries[i].fclk_mhz > max_clk_data.fclk_mhz) in build_synthetic_soc_states()
368 max_clk_data.fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz; in build_synthetic_soc_states()
369 if (bw_params->clk_table.entries[i].memclk_mhz > max_clk_data.memclk_mhz) in build_synthetic_soc_states()
370 max_clk_data.memclk_mhz = bw_params->clk_table.entries[i].memclk_mhz; in build_synthetic_soc_states()
371 if (bw_params->clk_table.entries[i].dispclk_mhz > max_clk_data.dispclk_mhz) in build_synthetic_soc_states()
372 max_clk_data.dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in build_synthetic_soc_states()
373 if (bw_params->clk_table.entries[i].dppclk_mhz > max_clk_data.dppclk_mhz) in build_synthetic_soc_states()
374 max_clk_data.dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in build_synthetic_soc_states()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/ |
| H A D | dcn302_fpu.c | 220 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn302_fpu_update_bw_bounding_box()
224 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn302_fpu_update_bw_bounding_box()
225 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn302_fpu_update_bw_bounding_box()
226 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn302_fpu_update_bw_bounding_box()
227 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn302_fpu_update_bw_bounding_box()
228 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn302_fpu_update_bw_bounding_box()
229 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn302_fpu_update_bw_bounding_box()
230 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn302_fpu_update_bw_bounding_box()
231 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn302_fpu_update_bw_bounding_box()
258 num_uclk_states = bw_params->clk_table.num_entries; in dcn302_fpu_update_bw_bounding_box()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/ |
| H A D | dcn303_fpu.c | 216 if (bw_params->clk_table.entries[0].memclk_mhz) { in dcn303_fpu_update_bw_bounding_box()
220 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn303_fpu_update_bw_bounding_box()
221 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn303_fpu_update_bw_bounding_box()
222 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz) in dcn303_fpu_update_bw_bounding_box()
223 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz; in dcn303_fpu_update_bw_bounding_box()
224 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz) in dcn303_fpu_update_bw_bounding_box()
225 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz; in dcn303_fpu_update_bw_bounding_box()
226 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz) in dcn303_fpu_update_bw_bounding_box()
227 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz; in dcn303_fpu_update_bw_bounding_box()
252 num_uclk_states = bw_params->clk_table.num_entries; in dcn303_fpu_update_bw_bounding_box()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 184 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn314_update_bw_bounding_box_fpu() local
205 ASSERT(clk_table->num_entries); in dcn314_update_bw_bounding_box_fpu()
208 for (i = 0; i < clk_table->num_entries; ++i) { in dcn314_update_bw_bounding_box_fpu()
209 if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz) in dcn314_update_bw_bounding_box_fpu()
210 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz; in dcn314_update_bw_bounding_box_fpu()
211 if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz) in dcn314_update_bw_bounding_box_fpu()
212 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz; in dcn314_update_bw_bounding_box_fpu()
215 for (i = 0; i < clk_table->num_entries; i++) { in dcn314_update_bw_bounding_box_fpu()
218 if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn314_update_bw_bounding_box_fpu()
223 if (clk_table->num_entries == 1) { in dcn314_update_bw_bounding_box_fpu()
[all …]
|
| /openbmc/linux/drivers/clk/mmp/ |
| H A D | clk.c | 13 struct clk **clk_table; in mmp_clk_init() local
15 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); in mmp_clk_init()
16 if (!clk_table) in mmp_clk_init()
19 unit->clk_table = clk_table; in mmp_clk_init()
21 unit->clk_data.clks = clk_table; in mmp_clk_init()
44 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_rate_clks()
66 unit->clk_table[clks[i].id] = clk; in mmp_register_fixed_factor_clks()
92 unit->clk_table[clks[i].id] = clk; in mmp_register_general_gate_clks()
120 unit->clk_table[clks[i].id] = clk; in mmp_register_gate_clks()
148 unit->clk_table[clks[i].id] = clk; in mmp_register_mux_clks()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega10_processpptables.c | 571 phm_ppt_v1_clock_voltage_dependency_table *clk_table; in get_socclk_voltage_dependency_table() local
576 clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries), in get_socclk_voltage_dependency_table()
578 if (!clk_table) in get_socclk_voltage_dependency_table()
581 clk_table->count = (uint32_t)clk_dep_table->ucNumEntries; in get_socclk_voltage_dependency_table()
584 clk_table->entries[i].vddInd = in get_socclk_voltage_dependency_table()
586 clk_table->entries[i].clk = in get_socclk_voltage_dependency_table()
590 *pp_vega10_clk_dep_table = clk_table; in get_socclk_voltage_dependency_table()
637 *clk_table; in get_gfxclk_voltage_dependency_table() local
643 clk_table = kzalloc(struct_size(clk_table, entries, clk_dep_table->ucNumEntries), in get_gfxclk_voltage_dependency_table()
645 if (!clk_table) in get_gfxclk_voltage_dependency_table()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | smu_v13_0_5_ppt.c | 621 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v13_0_5_get_dpm_level_count() local
625 *count = clk_table->NumSocClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
628 *count = clk_table->VcnClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
631 *count = clk_table->VcnClkLevelsEnabled; in smu_v13_0_5_get_dpm_level_count()
634 *count = clk_table->NumDfPstatesEnabled; in smu_v13_0_5_get_dpm_level_count()
637 *count = clk_table->NumDfPstatesEnabled; in smu_v13_0_5_get_dpm_level_count()
651 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v13_0_5_get_dpm_freq_by_index() local
653 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_5_get_dpm_freq_by_index()
658 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v13_0_5_get_dpm_freq_by_index()
660 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_5_get_dpm_freq_by_index()
[all …]
|
| H A D | smu_v13_0_4_ppt.c | 429 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in smu_v13_0_4_get_dpm_freq_by_index() local
431 if (!clk_table || clk_type >= SMU_CLK_COUNT) in smu_v13_0_4_get_dpm_freq_by_index()
436 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
438 *freq = clk_table->SocClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
441 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
443 *freq = clk_table->VClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
446 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
448 *freq = clk_table->DClocks[dpm_level]; in smu_v13_0_4_get_dpm_freq_by_index()
452 if (dpm_level >= clk_table->NumDfPstatesEnabled) in smu_v13_0_4_get_dpm_freq_by_index()
454 *freq = clk_table->DfPstateTable[dpm_level].MemClk; in smu_v13_0_4_get_dpm_freq_by_index()
[all …]
|
| H A D | yellow_carp_ppt.c | 755 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in yellow_carp_get_dpm_level_count() local
759 *count = clk_table->NumSocClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
762 *count = clk_table->VcnClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
765 *count = clk_table->VcnClkLevelsEnabled; in yellow_carp_get_dpm_level_count()
768 *count = clk_table->NumDfPstatesEnabled; in yellow_carp_get_dpm_level_count()
771 *count = clk_table->NumDfPstatesEnabled; in yellow_carp_get_dpm_level_count()
785 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in yellow_carp_get_dpm_freq_by_index() local
787 if (!clk_table || clk_type >= SMU_CLK_COUNT) in yellow_carp_get_dpm_freq_by_index()
792 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in yellow_carp_get_dpm_freq_by_index()
794 *freq = clk_table->SocClocks[dpm_level]; in yellow_carp_get_dpm_freq_by_index()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 97 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn3_init_single_clock()
133 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
139 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn3_init_clocks()
144 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn3_init_clocks()
150 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn3_init_clocks()
155 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz, in dcn3_init_clocks()
160 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz, in dcn3_init_clocks()
270 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_update_clocks()
368 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_set_hard_min_memclk()
371 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz); in dcn3_set_hard_min_memclk()
[all …]
|
| /openbmc/linux/drivers/clk/hisilicon/ |
| H A D | clk.c | 31 struct clk **clk_table; in hisi_clk_alloc() local
45 clk_table = devm_kmalloc_array(&pdev->dev, nr_clks, in hisi_clk_alloc()
46 sizeof(*clk_table), in hisi_clk_alloc()
48 if (!clk_table) in hisi_clk_alloc()
51 clk_data->clk_data.clks = clk_table; in hisi_clk_alloc()
62 struct clk **clk_table; in hisi_clk_init() local
76 clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL); in hisi_clk_init()
77 if (!clk_table) in hisi_clk_init()
80 clk_data->clk_data.clks = clk_table; in hisi_clk_init()
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 181 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz; in dcn32_build_wm_range_table_fpu()
182 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
192 …e.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfcl… in dcn32_build_wm_range_table_fpu()
194 if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz) in dcn32_build_wm_range_table_fpu()
195 setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz; in dcn32_build_wm_range_table_fpu()
233 …params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memcl… in dcn32_build_wm_range_table_fpu()
235 …params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memcl… in dcn32_build_wm_range_table_fpu()
237 …params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memcl… in dcn32_build_wm_range_table_fpu()
239 …params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memcl… in dcn32_build_wm_range_table_fpu()
2164 …int min_dram_speed_mts_offset = dc->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_l… in dcn32_calculate_wm_and_dlg_fpu()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 327 struct clk_limit_table *clk_table = &bw_params->clk_table; in dcn301_update_bw_bounding_box() local
340 ASSERT(clk_table->num_entries); in dcn301_update_bw_bounding_box()
341 for (i = 0; i < clk_table->num_entries; i++) { in dcn301_update_bw_bounding_box()
344 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn301_update_bw_bounding_box()
351 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn301_update_bw_bounding_box()
352 s[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in dcn301_update_bw_bounding_box()
353 s[i].socclk_mhz = clk_table->entries[i].socclk_mhz; in dcn301_update_bw_bounding_box()
354 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2; in dcn301_update_bw_bounding_box()
367 if (clk_table->num_entries) { in dcn301_update_bw_bounding_box()
368 dcn3_01_soc.num_states = clk_table->num_entries; in dcn301_update_bw_bounding_box()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 259 .clk_table = {
366 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn316_build_watermark_ranges()
369 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn316_build_watermark_ranges()
505 bw_params->clk_table.num_entries = j + 1; in dcn316_clk_mgr_helper_populate_bw_params()
516 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in dcn316_clk_mgr_helper_populate_bw_params()
519 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk; in dcn316_clk_mgr_helper_populate_bw_params()
520 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; in dcn316_clk_mgr_helper_populate_bw_params()
521 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage; in dcn316_clk_mgr_helper_populate_bw_params()
524 bw_params->clk_table.entries[i].wck_ratio = 2; in dcn316_clk_mgr_helper_populate_bw_params()
527 bw_params->clk_table.entries[i].wck_ratio = 4; in dcn316_clk_mgr_helper_populate_bw_params()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.c | 337 .clk_table = {
444 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn31_build_watermark_ranges()
447 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn31_build_watermark_ranges()
582 bw_params->clk_table.num_entries = j + 1; in dcn31_clk_mgr_helper_populate_bw_params()
593 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in dcn31_clk_mgr_helper_populate_bw_params()
594 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk; in dcn31_clk_mgr_helper_populate_bw_params()
595 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk; in dcn31_clk_mgr_helper_populate_bw_params()
596 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage; in dcn31_clk_mgr_helper_populate_bw_params()
599 bw_params->clk_table.entries[i].wck_ratio = 2; in dcn31_clk_mgr_helper_populate_bw_params()
602 bw_params->clk_table.entries[i].wck_ratio = 4; in dcn31_clk_mgr_helper_populate_bw_params()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 409 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in vg_build_watermark_ranges()
412 bw_params->clk_table.entries[i].dcfclk_mhz; in vg_build_watermark_ranges()
493 .clk_table = {
584 bw_params->clk_table.num_entries = j + 1; in vg_clk_mgr_helper_populate_bw_params()
586 for (i = 0; i < bw_params->clk_table.num_entries - 1; i++, j--) { in vg_clk_mgr_helper_populate_bw_params()
587 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
588 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk; in vg_clk_mgr_helper_populate_bw_params()
589 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage; in vg_clk_mgr_helper_populate_bw_params()
590 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfP… in vg_clk_mgr_helper_populate_bw_params()
592 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk; in vg_clk_mgr_helper_populate_bw_params()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 144 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]); in dcn32_init_single_clock()
159 …struct clk_limit_num_entries *num_entries_per_clk = &clk_mgr_base->bw_params->clk_table.num_entrie… in dcn32_init_clocks()
183 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn32_init_clocks()
189 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz, in dcn32_init_clocks()
196 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz, in dcn32_init_clocks()
204 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz, in dcn32_init_clocks()
219 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz in dcn32_init_clocks()
221 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz in dcn32_init_clocks()
225 if (clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz > 1950) in dcn32_init_clocks()
226 clk_mgr_base->bw_params->clk_table.entries[i].dispclk_mhz = 1950; in dcn32_init_clocks()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 477 …ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcf… in build_watermark_ranges()
479 …ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_… in build_watermark_ranges()
577 .clk_table = {
663 bw_params->clk_table.num_entries = j + 1; in rn_clk_mgr_helper_populate_bw_params()
665 for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) { in rn_clk_mgr_helper_populate_bw_params()
666 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
667 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq; in rn_clk_mgr_helper_populate_bw_params()
668 bw_params->clk_table.entries[i].voltage = clock_table->FClocks[j].Vol; in rn_clk_mgr_helper_populate_bw_params()
669 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FCl… in rn_clk_mgr_helper_populate_bw_params()
670 bw_params->clk_table.entries[i].socclk_mhz = find_socclk_for_voltage(clock_table, in rn_clk_mgr_helper_populate_bw_params()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | vangogh_ppt.c | 542 DpmClocks_t *clk_table = smu->smu_table.clocks_table; in vangogh_get_dpm_clk_limited() local
544 if (!clk_table || clk_type >= SMU_CLK_COUNT) in vangogh_get_dpm_clk_limited()
549 if (dpm_level >= clk_table->NumSocClkLevelsEnabled) in vangogh_get_dpm_clk_limited()
551 *freq = clk_table->SocClocks[dpm_level]; in vangogh_get_dpm_clk_limited()
554 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in vangogh_get_dpm_clk_limited()
556 *freq = clk_table->VcnClocks[dpm_level].vclk; in vangogh_get_dpm_clk_limited()
559 if (dpm_level >= clk_table->VcnClkLevelsEnabled) in vangogh_get_dpm_clk_limited()
561 *freq = clk_table->VcnClocks[dpm_level].dclk; in vangogh_get_dpm_clk_limited()
565 if (dpm_level >= clk_table->NumDfPstatesEnabled) in vangogh_get_dpm_clk_limited()
567 *freq = clk_table->DfPstateTable[dpm_level].memclk; in vangogh_get_dpm_clk_limited()
[all …]
|
| /openbmc/linux/drivers/clk/axis/ |
| H A D | clk-artpec6.c | 20 struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS]; member
56 clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
107 clkdata->clk_data.clks = clkdata->clk_table; in of_artpec6_clkctrl_setup()
121 struct clk **clks = clkdata->clk_table; in artpec6_clkctrl_probe()
|