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Searched refs:cfg0 (Results 1 – 25 of 50) sorted by relevance

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/openbmc/linux/drivers/edac/
H A Docteon_edac-lmc.c40 union cvmx_lmcx_mem_cfg0 cfg0; in octeon_lmc_edac_poll() local
44 cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx)); in octeon_lmc_edac_poll()
45 if (cfg0.s.sec_err || cfg0.s.ded_err) { in octeon_lmc_edac_poll()
54 if (cfg0.s.sec_err) { in octeon_lmc_edac_poll()
57 cfg0.s.sec_err = -1; /* Done, re-arm */ in octeon_lmc_edac_poll()
61 if (cfg0.s.ded_err) { in octeon_lmc_edac_poll()
64 cfg0.s.ded_err = -1; /* Done, re-arm */ in octeon_lmc_edac_poll()
68 cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx), cfg0.u64); in octeon_lmc_edac_poll()
238 union cvmx_lmcx_mem_cfg0 cfg0; in octeon_lmc_edac_probe() local
240 cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(0)); in octeon_lmc_edac_probe()
[all …]
/openbmc/linux/arch/mips/ralink/
H A Dmt7620.c223 u32 cfg0; in prom_soc_init() local
231 cfg0 = __raw_readl(MT7620_SYSC_BASE + SYSC_REG_SYSTEM_CONFIG0); in prom_soc_init()
233 dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; in prom_soc_init()
235 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & in prom_soc_init()
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramnv10.c31 u32 cfg0 = nvkm_rd32(device, 0x100200); in nv10_ram_new() local
34 if (cfg0 & 0x00000001) in nv10_ram_new()
/openbmc/u-boot/drivers/video/sunxi/
H A Dtve_common.c22 writel(SUNXI_TVE_CFG0_VGA, &tve->cfg0); in tvencoder_mode_set()
34 writel(SUNXI_TVE_CFG0_PAL, &tve->cfg0); in tvencoder_mode_set()
60 writel(SUNXI_TVE_CFG0_NTSC, &tve->cfg0); in tvencoder_mode_set()
/openbmc/qemu/hw/misc/
H A Dmps2-scc.c154 r = s->cfg0; in mps2_scc_read()
255 s->cfg0 = value; in mps2_scc_write()
257 qemu_set_irq(s->remap, s->cfg0 & 1); in mps2_scc_write()
366 s->cfg0 = s->cfg0_reset; in mps2_scc_reset()
438 VMSTATE_UINT32(cfg0, MPS2SCC),
/openbmc/linux/arch/loongarch/mm/
H A Dcache.c94 #define populate_cache_properties(cfg0, cdesc, level, leaf) \ argument
102 if (cfg0 & LXIUPRIV) \
104 if (cfg0 & LXIUINCL) \
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt76x2/
H A Dphy.c187 u32 cfg0, cfg1; in mt76x2_configure_tx_delay() local
190 cfg0 = bw ? 0x000b0c01 : 0x00101101; in mt76x2_configure_tx_delay()
193 cfg0 = bw ? 0x000b0b01 : 0x00101001; in mt76x2_configure_tx_delay()
196 mt76_wr(dev, MT_TX_SW_CFG0, cfg0); in mt76x2_configure_tx_delay()
/openbmc/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_fimc.c1011 u32 cfg0, cfg1; in fimc_start() local
1023 cfg0 = fimc_read(ctx, EXYNOS_MSCTRL); in fimc_start()
1024 cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK; in fimc_start()
1025 cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY; in fimc_start()
1026 fimc_write(ctx, cfg0, EXYNOS_MSCTRL); in fimc_start()
1031 cfg0 = fimc_read(ctx, EXYNOS_CIIMGCPT); in fimc_start()
1032 cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC; in fimc_start()
1033 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC; in fimc_start()
1044 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN; in fimc_start()
1045 fimc_write(ctx, cfg0, EXYNOS_CIIMGCPT); in fimc_start()
/openbmc/linux/drivers/infiniband/hw/erdma/
H A Derdma_hw.h240 u32 cfg0; member
268 u32 cfg0; member
331 u32 cfg0; member
/openbmc/qemu/include/hw/misc/
H A Dmps2-scc.h48 uint32_t cfg0; member
/openbmc/u-boot/drivers/pci/
H A Dpcie_layerscape.c266 *paddress = pcie->cfg0 + offset; in ls_pcie_conf_address()
516 pcie->cfg0 = map_physmem(pcie->cfg_res.start, in ls_pcie_probe()
519 pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2; in ls_pcie_probe()
525 (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0, in ls_pcie_probe()
H A Dpcie_layerscape.h142 void __iomem *cfg0; member
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfdt.c164 u32 cfg0 = in_be32(&cpc->cpccfg0); in ft_fixup_l3cache() local
166 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; in ft_fixup_l3cache()
167 num_ways = CPC_CFG0_NUM_WAYS(cfg0); in ft_fixup_l3cache()
168 line_size = CPC_CFG0_LINE_SZ(cfg0); in ft_fixup_l3cache()
/openbmc/linux/drivers/net/phy/
H A Ddp83640.c116 int cfg0; member
553 u16 cfg0 = 0, ver; in enable_status_frames() local
556 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG; in enable_status_frames()
562 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0); in enable_status_frames()
636 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val; in recalibrate() local
652 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0); in recalibrate()
657 cfg0 = ext_read(master, PAGE5, PSF_CFG0); in recalibrate()
729 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0); in recalibrate()
730 ext_write(0, master, PAGE5, PSF_CFG0, cfg0); in recalibrate()
/openbmc/linux/arch/sparc/include/asm/
H A Dsbi.h20 /* 0x0010 */ u32 cfg0; /* Slot0 config reg */ member
/openbmc/linux/drivers/soc/qcom/
H A Dqcom-geni-se.c434 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; in geni_se_config_packing() local
462 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT); in geni_se_config_packing()
466 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); in geni_se_config_packing()
470 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); in geni_se_config_packing()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun50i_h6.c127 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0) in mbus_configure_port() local
135 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1); in mbus_configure_port()
136 writel(cfg0, &mctl_com->master[port].cfg0); in mbus_configure_port()
H A Ddram_sunxi_dw.c92 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0) in mbus_configure_port() local
100 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1); in mbus_configure_port()
101 writel(cfg0, &mctl_com->mcr[port][0]); in mbus_configure_port()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dtve.h29 u32 cfg0; /* 0x004 */ member
/openbmc/linux/sound/pci/au88x0/
H A Dau88x0_core.c1096 dma->cfg0 = 0; in vortex_adbdma_setbuffers()
1109 dma->cfg0 |= 0x12000000; in vortex_adbdma_setbuffers()
1117 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize - 1); in vortex_adbdma_setbuffers()
1124 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc); in vortex_adbdma_setbuffers()
1134 hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG0 + (adbdma << 3), dma->cfg0); in vortex_adbdma_setbuffers()
1375 dma->cfg0 = 0; in vortex_wtdma_setbuffers()
1387 dma->cfg0 |= 0x12000000; in vortex_wtdma_setbuffers()
1394 dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize-1); in vortex_wtdma_setbuffers()
1400 dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc); in vortex_wtdma_setbuffers()
1405 hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + (wtdma << 3), dma->cfg0); in vortex_wtdma_setbuffers()
/openbmc/linux/drivers/mtd/nand/raw/
H A Dqcom_nandc.c317 __le32 cfg0; member
534 u32 cfg0, cfg1; member
713 return &regs->cfg0; in offset_to_nandc_reg()
814 u32 cmd, cfg0, cfg1, ecc_bch_cfg; in update_rw_regs() local
827 cfg0 = (host->cfg0 & ~(7U << CW_PER_PAGE)) | in update_rw_regs()
833 cfg0 = (host->cfg0_raw & ~(7U << CW_PER_PAGE)) | in update_rw_regs()
841 nandc_set_reg(chip, NAND_DEV0_CFG0, cfg0); in update_rw_regs()
1875 host->cfg0 &= ~(SPARE_SIZE_BYTES_MASK | UD_SIZE_BYTES_MASK); in qcom_nandc_codeword_fixup()
1876 host->cfg0 |= host->spare_bytes << SPARE_SIZE_BYTES | in qcom_nandc_codeword_fixup()
2488 host->cfg0 = (cwperpage - 1) << CW_PER_PAGE in qcom_nand_attach_chip()
[all …]
/openbmc/linux/include/linux/
H A Dswitchtec.h231 struct partition_info cfg0; member
258 struct partition_info cfg0; member
/openbmc/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8710b.c590 u32 cfg0, cfg2, vendor; in rtl8710bu_identify_chip() local
600 cfg0 = rtl8710b_read_syson_reg(priv, REG_SYS_SYSTEM_CFG0_8710B); in rtl8710bu_identify_chip()
601 priv->chip_cut = cfg0 & 0xf; in rtl8710bu_identify_chip()
603 if (cfg0 & BIT(16)) { in rtl8710bu_identify_chip()
608 vendor = u32_get_bits(cfg0, 0xc0); in rtl8710bu_identify_chip()
/openbmc/linux/drivers/pci/controller/
H A Dpcie-altera.c324 u8 cfg0 = read ? pcie->pcie_data->cfgrd0 : pcie->pcie_data->cfgwr0; in get_tlp_header() local
329 cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1; in get_tlp_header()
331 cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1; in get_tlp_header()
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dsi_vbt.c298 u16 cfg0, cfg1; in chv_exec_gpio() local
337 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); in chv_exec_gpio()
342 vlv_iosf_sb_write(dev_priv, port, cfg0, in chv_exec_gpio()

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