1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
2a439fe51SSam Ravnborg /*
3a439fe51SSam Ravnborg * sbi.h: SBI (Sbus Interface on sun4d) definitions
4a439fe51SSam Ravnborg *
5a439fe51SSam Ravnborg * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
6a439fe51SSam Ravnborg */
7a439fe51SSam Ravnborg
8a439fe51SSam Ravnborg #ifndef _SPARC_SBI_H
9a439fe51SSam Ravnborg #define _SPARC_SBI_H
10a439fe51SSam Ravnborg
11a439fe51SSam Ravnborg #include <asm/obio.h>
12a439fe51SSam Ravnborg
13a439fe51SSam Ravnborg /* SBI */
14a439fe51SSam Ravnborg struct sbi_regs {
15a439fe51SSam Ravnborg /* 0x0000 */ u32 cid; /* Component ID */
16a439fe51SSam Ravnborg /* 0x0004 */ u32 ctl; /* Control */
17a439fe51SSam Ravnborg /* 0x0008 */ u32 status; /* Status */
18a439fe51SSam Ravnborg u32 _unused1;
19a439fe51SSam Ravnborg
20a439fe51SSam Ravnborg /* 0x0010 */ u32 cfg0; /* Slot0 config reg */
21a439fe51SSam Ravnborg /* 0x0014 */ u32 cfg1; /* Slot1 config reg */
22a439fe51SSam Ravnborg /* 0x0018 */ u32 cfg2; /* Slot2 config reg */
23a439fe51SSam Ravnborg /* 0x001c */ u32 cfg3; /* Slot3 config reg */
24a439fe51SSam Ravnborg
25a439fe51SSam Ravnborg /* 0x0020 */ u32 stb0; /* Streaming buf control for slot 0 */
26a439fe51SSam Ravnborg /* 0x0024 */ u32 stb1; /* Streaming buf control for slot 1 */
27a439fe51SSam Ravnborg /* 0x0028 */ u32 stb2; /* Streaming buf control for slot 2 */
28a439fe51SSam Ravnborg /* 0x002c */ u32 stb3; /* Streaming buf control for slot 3 */
29a439fe51SSam Ravnborg
30a439fe51SSam Ravnborg /* 0x0030 */ u32 intr_state; /* Interrupt state */
31a439fe51SSam Ravnborg /* 0x0034 */ u32 intr_tid; /* Interrupt target ID */
32a439fe51SSam Ravnborg /* 0x0038 */ u32 intr_diag; /* Interrupt diagnostics */
33a439fe51SSam Ravnborg };
34a439fe51SSam Ravnborg
35a439fe51SSam Ravnborg #define SBI_CID 0x02800000
36a439fe51SSam Ravnborg #define SBI_CTL 0x02800004
37a439fe51SSam Ravnborg #define SBI_STATUS 0x02800008
38a439fe51SSam Ravnborg #define SBI_CFG0 0x02800010
39a439fe51SSam Ravnborg #define SBI_CFG1 0x02800014
40a439fe51SSam Ravnborg #define SBI_CFG2 0x02800018
41a439fe51SSam Ravnborg #define SBI_CFG3 0x0280001c
42a439fe51SSam Ravnborg #define SBI_STB0 0x02800020
43a439fe51SSam Ravnborg #define SBI_STB1 0x02800024
44a439fe51SSam Ravnborg #define SBI_STB2 0x02800028
45a439fe51SSam Ravnborg #define SBI_STB3 0x0280002c
46a439fe51SSam Ravnborg #define SBI_INTR_STATE 0x02800030
47a439fe51SSam Ravnborg #define SBI_INTR_TID 0x02800034
48a439fe51SSam Ravnborg #define SBI_INTR_DIAG 0x02800038
49a439fe51SSam Ravnborg
50a439fe51SSam Ravnborg /* Burst bits for 8, 16, 32, 64 are in cfgX registers at bits 2, 3, 4, 5 respectively */
51a439fe51SSam Ravnborg #define SBI_CFG_BURST_MASK 0x0000001e
52a439fe51SSam Ravnborg
53a439fe51SSam Ravnborg /* How to make devid from sbi no */
54a439fe51SSam Ravnborg #define SBI2DEVID(sbino) ((sbino<<4)|2)
55a439fe51SSam Ravnborg
56a439fe51SSam Ravnborg /* intr_state has 4 bits for slots 0 .. 3 and these bits are repeated for each sbus irq level
57a439fe51SSam Ravnborg *
58a439fe51SSam Ravnborg * +-------+-------+-------+-------+-------+-------+-------+-------+
59a439fe51SSam Ravnborg * SBUS IRQ LEVEL | 7 | 6 | 5 | 4 | 3 | 2 | 1 | |
60a439fe51SSam Ravnborg * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ Reser |
61a439fe51SSam Ravnborg * SLOT # |3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0| ved |
62a439fe51SSam Ravnborg * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------+
63a439fe51SSam Ravnborg * Bits 31 27 23 19 15 11 7 3 0
64a439fe51SSam Ravnborg */
65a439fe51SSam Ravnborg
66a439fe51SSam Ravnborg
67a439fe51SSam Ravnborg #ifndef __ASSEMBLY__
68a439fe51SSam Ravnborg
acquire_sbi(int devid,int mask)69a439fe51SSam Ravnborg static inline int acquire_sbi(int devid, int mask)
70a439fe51SSam Ravnborg {
71a439fe51SSam Ravnborg __asm__ __volatile__ ("swapa [%2] %3, %0" :
72a439fe51SSam Ravnborg "=r" (mask) :
73a439fe51SSam Ravnborg "0" (mask),
74a439fe51SSam Ravnborg "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
75a439fe51SSam Ravnborg "i" (ASI_M_CTL));
76a439fe51SSam Ravnborg return mask;
77a439fe51SSam Ravnborg }
78a439fe51SSam Ravnborg
release_sbi(int devid,int mask)79a439fe51SSam Ravnborg static inline void release_sbi(int devid, int mask)
80a439fe51SSam Ravnborg {
81a439fe51SSam Ravnborg __asm__ __volatile__ ("sta %0, [%1] %2" : :
82a439fe51SSam Ravnborg "r" (mask),
83a439fe51SSam Ravnborg "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
84a439fe51SSam Ravnborg "i" (ASI_M_CTL));
85a439fe51SSam Ravnborg }
86a439fe51SSam Ravnborg
set_sbi_tid(int devid,int targetid)87a439fe51SSam Ravnborg static inline void set_sbi_tid(int devid, int targetid)
88a439fe51SSam Ravnborg {
89a439fe51SSam Ravnborg __asm__ __volatile__ ("sta %0, [%1] %2" : :
90a439fe51SSam Ravnborg "r" (targetid),
91a439fe51SSam Ravnborg "r" (ECSR_DEV_BASE(devid) | SBI_INTR_TID),
92a439fe51SSam Ravnborg "i" (ASI_M_CTL));
93a439fe51SSam Ravnborg }
94a439fe51SSam Ravnborg
get_sbi_ctl(int devid,int cfgno)95a439fe51SSam Ravnborg static inline int get_sbi_ctl(int devid, int cfgno)
96a439fe51SSam Ravnborg {
97a439fe51SSam Ravnborg int cfg;
98a439fe51SSam Ravnborg
99a439fe51SSam Ravnborg __asm__ __volatile__ ("lda [%1] %2, %0" :
100a439fe51SSam Ravnborg "=r" (cfg) :
101a439fe51SSam Ravnborg "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
102a439fe51SSam Ravnborg "i" (ASI_M_CTL));
103a439fe51SSam Ravnborg return cfg;
104a439fe51SSam Ravnborg }
105a439fe51SSam Ravnborg
set_sbi_ctl(int devid,int cfgno,int cfg)106a439fe51SSam Ravnborg static inline void set_sbi_ctl(int devid, int cfgno, int cfg)
107a439fe51SSam Ravnborg {
108a439fe51SSam Ravnborg __asm__ __volatile__ ("sta %0, [%1] %2" : :
109a439fe51SSam Ravnborg "r" (cfg),
110a439fe51SSam Ravnborg "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
111a439fe51SSam Ravnborg "i" (ASI_M_CTL));
112a439fe51SSam Ravnborg }
113a439fe51SSam Ravnborg
114a439fe51SSam Ravnborg #endif /* !__ASSEMBLY__ */
115a439fe51SSam Ravnborg
116a439fe51SSam Ravnborg #endif /* !(_SPARC_SBI_H) */
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