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/openbmc/qemu/migration/
H A Dpage_cache.c45 PageCache *cache; in cache_init() local
61 cache = g_try_malloc(sizeof(*cache)); in cache_init()
62 if (!cache) { in cache_init()
66 cache->page_size = page_size; in cache_init()
67 cache->num_items = 0; in cache_init()
68 cache->max_num_items = num_pages; in cache_init()
70 trace_migration_pagecache_init(cache->max_num_items); in cache_init()
73 cache->page_cache = g_try_malloc((cache->max_num_items) * in cache_init()
74 sizeof(*cache->page_cache)); in cache_init()
75 if (!cache->page_cache) { in cache_init()
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/openbmc/u-boot/arch/arm/dts/
H A Dk3-am654.dtsi41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
43 i-cache-sets = <256>;
44 d-cache-size = <0x8000>;
45 d-cache-line-size = <64>;
46 d-cache-sets = <128>;
47 next-level-cache = <&L2_0>;
55 i-cache-size = <0x8000>;
56 i-cache-line-size = <64>;
57 i-cache-sets = <256>;
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/openbmc/u-boot/arch/x86/lib/
H A Dmrccache.c21 struct mrc_data_container *cache) in next_mrc_block() argument
24 u32 mrc_size = sizeof(*cache) + cache->data_size; in next_mrc_block()
25 u8 *region_ptr = (u8 *)cache; in next_mrc_block()
37 static int is_mrc_cache(struct mrc_data_container *cache) in is_mrc_cache() argument
39 return cache && (cache->signature == MRC_DATA_SIGNATURE); in is_mrc_cache()
44 struct mrc_data_container *cache, *next; in mrccache_find_current() local
50 cache = NULL; in mrccache_find_current()
56 cache = next; in mrccache_find_current()
68 if (cache->checksum != compute_ip_checksum(cache->data, in mrccache_find_current()
69 cache->data_size)) { in mrccache_find_current()
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/openbmc/qemu/include/exec/
H A Dmemory_ldst_cached.h.inc27 static inline uint16_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
30 assert(addr < cache->len && 2 <= cache->len - addr);
31 fuzz_dma_read_cb(cache->xlat + addr, 2, cache->mrs.mr);
32 if (likely(cache->ptr)) {
33 return LD_P(uw)(cache->ptr + addr);
35 return ADDRESS_SPACE_LD_CACHED_SLOW(uw)(cache, addr, attrs, result);
39 static inline uint32_t ADDRESS_SPACE_LD_CACHED(l)(MemoryRegionCache *cache,
42 assert(addr < cache->len && 4 <= cache->len - addr);
43 fuzz_dma_read_cb(cache->xlat + addr, 4, cache->mrs.mr);
44 if (likely(cache->ptr)) {
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/openbmc/qemu/tests/qemu-iotests/
H A D157.out6 Testing: cache='writeback' wce=''
8 Testing: cache='writeback' wce=',write-cache=auto'
10 Testing: cache='writeback' wce=',write-cache=on'
12 Testing: cache='writeback' wce=',write-cache=off'
14 Testing: cache='writethrough' wce=''
16 Testing: cache='writethrough' wce=',write-cache=auto'
18 Testing: cache='writethrough' wce=',write-cache=on'
20 Testing: cache='writethrough' wce=',write-cache=off'
H A D14273 echo === Simple test for all cache modes ===
76 run_qemu -drive file="$TEST_IMG",cache=none
77 run_qemu -drive file="$TEST_IMG",cache=directsync
78 run_qemu -drive file="$TEST_IMG",cache=writeback
79 run_qemu -drive file="$TEST_IMG",cache=writethrough
80 run_qemu -drive file="$TEST_IMG",cache=unsafe
81 run_qemu -drive file="$TEST_IMG",cache=invalid_value
84 echo === Check inheritance of cache modes ===
96 …echo "$hmp_cmds" | run_qemu -drive "$files","$ids",cache.direct=on | grep -e "Cache" -e "[Cc]annot…
98 …echo "$hmp_cmds" | run_qemu -drive "$files","$ids",file.cache.direct=on | grep -e "Cache" -e "[Cc]…
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H A D142.out6 === Simple test for all cache modes ===
8 Testing: -drive file=TEST_DIR/t.qcow2,cache=none
12 Testing: -drive file=TEST_DIR/t.qcow2,cache=directsync
16 Testing: -drive file=TEST_DIR/t.qcow2,cache=writeback
20 Testing: -drive file=TEST_DIR/t.qcow2,cache=writethrough
24 Testing: -drive file=TEST_DIR/t.qcow2,cache=unsafe
28 Testing: -drive file=TEST_DIR/t.qcow2,cache=invalid_value
29 QEMU_PROG: -drive file=TEST_DIR/t.qcow2,cache=invalid_value: invalid cache option
32 === Check inheritance of cache modes ===
35 --- Configure cache modes on the command line ---
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H A D103.out8 qemu-io: can't open device TEST_DIR/t.IMGFMT: cache-size, l2-cache-size and refcount-cache-size may…
9 qemu-io: can't open device TEST_DIR/t.IMGFMT: l2-cache-size may not exceed cache-size
10 qemu-io: can't open device TEST_DIR/t.IMGFMT: refcount-cache-size may not exceed cache-size
11 qemu-io: can't open device TEST_DIR/t.IMGFMT: cache-size, l2-cache-size and refcount-cache-size may…
12 qemu-io: can't open device TEST_DIR/t.IMGFMT: L2 cache entry size must be a power of two between 51…
13 qemu-io: can't open device TEST_DIR/t.IMGFMT: L2 cache entry size must be a power of two between 51…
14 qemu-io: can't open device TEST_DIR/t.IMGFMT: L2 cache entry size must be a power of two between 51…
33 === Testing minimal L2 cache and COW ===
/openbmc/qemu/contrib/plugins/
H A Dcache.c92 void (*update_hit)(Cache *cache, int set, int blk);
93 void (*update_miss)(Cache *cache, int set, int blk);
95 void (*metadata_init)(Cache *cache);
96 void (*metadata_destroy)(Cache *cache);
140 static void lru_priorities_init(Cache *cache) in lru_priorities_init() argument
144 for (i = 0; i < cache->num_sets; i++) { in lru_priorities_init()
145 cache->sets[i].lru_priorities = g_new0(uint64_t, cache->assoc); in lru_priorities_init()
146 cache->sets[i].lru_gen_counter = 0; in lru_priorities_init()
150 static void lru_update_blk(Cache *cache, int set_idx, int blk_idx) in lru_update_blk() argument
152 CacheSet *set = &cache->sets[set_idx]; in lru_update_blk()
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/openbmc/u-boot/doc/
H A DREADME.arm-caches1 Disabling I-cache:
4 Disabling D-cache:
7 Enabling I-cache:
10 Enabling D-cache:
14 - Implement enable_caches() for your platform and enable the I-cache and
15 D-cache from this function. This function is called immediately
18 Guidelines for Working with D-cache:
26 lines from the DMA buffer in the cache, subsequent cache-line replacements
29 into the cache while the DMA is going on.
33 come to the cache due to speculative memory access by the CPU. If this
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H A DREADME.mips22 writing back and invalidating cache lines. This leads to cache
24 re-initializes the cache. The more common uImage 'bootm' command does
27 [workaround] To avoid this cache incoherency,
29 2) fix dcache_disable() to do both flushing and disabling cache.
38 * Probe CPU types, I-/D-cache and TLB size etc. automatically
40 * Secondary cache support missing
48 * Due to cache initialization issues, the DRAM on board must be
49 initialized in board specific assembler language before the cache init
/openbmc/qemu/docs/
H A Dqcow2-cache.txt1 qcow2 L2/refcount cache configuration
12 performance significantly. However, setting the right cache sizes is
50 an L2 cache in memory to speed up disk access.
52 The size of the L2 cache can be configured, and setting the right
73 QEMU keeps a refcount cache to speed up I/O much like the
74 aforementioned L2 cache, and its size can also be configured.
77 Choosing the right cache sizes
79 In order to choose the cache sizes we need to know how they relate to
100 For example, 1MB of L2 cache is needed to cover every 8 GB of the virtual
105 The refcount cache is 4 times the cluster size by default. With the default
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H A Dxbzrle.txt15 be stored on the source. Those pages are stored in a dedicated cache
17 The larger the cache size the better the chances are that the page has already
18 been stored in the cache.
19 A small cache size will result in high cache miss rate.
45 retrieving the old page content from the cache (default size of 64MB). The
76 Keeping the hot pages in the cache is effective for decreasing cache
78 increase after each ram dirty bitmap sync. When a cache conflict is
79 detected, XBZRLE will only evict pages in the cache that are older than
91 3. Set the XBZRLE cache size - the cache size is in MBytes and should be a
92 power of 2. The cache default value is 64MBytes. (on source only)
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/openbmc/openbmc/poky/meta/recipes-core/glibc/ldconfig-native-2.12.1/
H A Dldconfig.patch6 cache.c | 11 +-
8 dl-cache.c | 235 ---------------------------------------------------------
9 dl-cache.h | 3
15 Index: ldconfig-native-2.12.1/cache.c
17 --- ldconfig-native-2.12.1.orig/cache.c
18 +++ ldconfig-native-2.12.1/cache.c
34 -#include <dl-cache.h>
36 +#include "dl-cache.h"
67 Index: ldconfig-native-2.12.1/dl-cache.c
69 --- ldconfig-native-2.12.1.orig/dl-cache.c
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/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dcache_v7_asm.S32 mov r10, #0 @ start clean at cache level 0
34 add r2, r10, r10, lsr #1 @ work out 3x current cache level
35 mov r1, r0, lsr r2 @ extract cache type bits from clidr
36 and r1, r1, #7 @ mask of the bits for current cache only
37 cmp r1, #2 @ see what cache we have at this level
38 blt skip @ skip if no cache, or just i-cache
39 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
42 and r2, r1, #7 @ extract the length of the cache lines
52 ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
54 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
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/openbmc/qemu/include/hw/virtio/
H A Dvirtio-access.h160 MemoryRegionCache *cache, in virtio_lduw_phys_cached() argument
164 return lduw_be_phys_cached(cache, pa); in virtio_lduw_phys_cached()
166 return lduw_le_phys_cached(cache, pa); in virtio_lduw_phys_cached()
170 MemoryRegionCache *cache, in virtio_ldl_phys_cached() argument
174 return ldl_be_phys_cached(cache, pa); in virtio_ldl_phys_cached()
176 return ldl_le_phys_cached(cache, pa); in virtio_ldl_phys_cached()
180 MemoryRegionCache *cache, in virtio_ldq_phys_cached() argument
184 return ldq_be_phys_cached(cache, pa); in virtio_ldq_phys_cached()
186 return ldq_le_phys_cached(cache, pa); in virtio_ldq_phys_cached()
190 MemoryRegionCache *cache, in virtio_stw_phys_cached() argument
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/openbmc/u-boot/arch/x86/cpu/quark/
H A Ddram.c21 struct mrc_data_container *cache; in prepare_mrc_cache() local
29 cache = mrccache_find_current(&entry); in prepare_mrc_cache()
30 if (!cache) in prepare_mrc_cache()
34 cache->data, cache->data_size, cache->checksum); in prepare_mrc_cache()
37 memcpy(&mrc_params->timings, cache->data, cache->data_size); in prepare_mrc_cache()
127 char *cache; in dram_init() local
153 cache = malloc(sizeof(struct mrc_timings)); in dram_init()
154 if (cache) { in dram_init()
155 memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings)); in dram_init()
156 gd->arch.mrc_output = cache; in dram_init()
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/nodejs/
H A Dnodejs-oe-cache-native_22.16.bb1 DESCRIPTION = "OE helper for manipulating npm cache"
6 file://oe-npm-cache \
17 sed -e 's!@@libdir@@!${libdir}!g' < '${UNPACKDIR}/oe-npm-cache' > '${B}/oe-npm-cache'
21 install -D -p -m 0755 ${B}/oe-npm-cache ${D}${bindir}/oe-npm-cache
/openbmc/openbmc/poky/scripts/postinst-intercepts/
H A Dupdate_gtk_immodules_cache10 > $D${libdir}/gtk-2.0/2.10.0/immodules.cache &&
11 sed -i -e "s:$D::" $D${libdir}/gtk-2.0/2.10.0/immodules.cache
12 chown root:root $D${libdir}/gtk-2.0/2.10.0/immodules.cache
16 > $D${libdir}/gtk-3.0/3.0.0/immodules.cache &&
17 sed -i -e "s:$D::" $D${libdir}/gtk-3.0/3.0.0/immodules.cache
18 chown root:root $D${libdir}/gtk-3.0/3.0.0/immodules.cache
/openbmc/openbmc/poky/documentation/dev-manual/
H A Ddisk-space.rst29 After multiple build iterations, the Shared State (sstate) cache can contain
30 multiple cache files for a given package, consuming a substantial amount of
33 The following command is a quick way to purge all the cache files which
36 find build/sstate-cache -type f -mtime +$DAYS -delete
38 The above command relies on the fact that BitBake touches the sstate cache
39 files as it accesses them, when it has write access to the cache.
42 with the ``noatime`` option for a read only cache.
45 command. It has the ability to purge all but the newest cache files on each
52 sstate-cache-management.py --remove-duplicated --cache-dir=sstate-cache
55 Run ``sstate-cache-management.sh`` for more details about this script.
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/openbmc/openbmc/poky/meta/recipes-graphics/menu-cache/files/
H A D0001-Support-gcc10-compilation.patch6 gcc10 now defaults to -fno-common, and with gcc10 menu-cache compilation fails like
8 /bin/ld: menu-merge.o:menu-cache-gen/menu-tags.h:167: multiple definition of `DirDirs'; main.o:menu…
9 /bin/ld: menu-merge.o:menu-cache-gen/menu-tags.h:164: multiple definition of `AppDirs'; main.o:menu…
10 /bin/ld: menu-merge.o:menu-cache-gen/menu-tags.h:52: multiple definition of `menuTag_Layout'; main.…
15 Upstream-Status: Submitted [https://github.com/lxde/menu-cache/pull/19]
18 menu-cache-gen/menu-tags.h | 55 ++++++++++++--------------------------
21 diff --git a/menu-cache-gen/menu-tags.h b/menu-cache-gen/menu-tags.h
23 --- a/menu-cache-gen/menu-tags.h
24 +++ b/menu-cache-gen/menu-tags.h
27 #include <menu-cache.h>
/openbmc/u-boot/drivers/block/
H A Dblkcache.c21 char *cache; member
60 const char *src = node->cache + (start - node->start) * blksz; in blkcache_read()
97 free(node->cache); in blkcache_fill()
98 node->cache = 0; in blkcache_fill()
104 node->cache = 0; in blkcache_fill()
107 if (!node->cache) { in blkcache_fill()
108 node->cache = malloc(bytes); in blkcache_fill()
109 if (!node->cache) { in blkcache_fill()
123 memcpy(node->cache, buffer, bytes); in blkcache_fill()
138 free(node->cache); in blkcache_invalidate()
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/openbmc/u-boot/arch/x86/lib/fsp/
H A Dfsp_common.c64 struct mrc_data_container *cache; in fsp_prepare_mrc_cache() local
72 cache = mrccache_find_current(&entry); in fsp_prepare_mrc_cache()
73 if (!cache) in fsp_prepare_mrc_cache()
77 cache->data, cache->data_size, cache->checksum); in fsp_prepare_mrc_cache()
79 return cache->data; in fsp_prepare_mrc_cache()
/openbmc/qemu/qapi/
H A Dmachine-common.json57 # topology settings (e.g., cache topology), and this special
70 # combination of cache level and cache type.
72 # @l1d: L1 data cache.
74 # @l1i: L1 instruction cache.
76 # @l2: L2 (unified) cache.
78 # @l3: L3 (unified) cache
90 # @cache: Cache name, which is the combination of cache level
91 # and cache type.
95 # topology container share the same cache.
101 'cache': 'CacheLevelAndType',
/openbmc/openbmc/poky/bitbake/lib/bb/
H A Dchecksum.py15 from bb.cache import MultiProcessCache
24 cache = {} variable in FileMtimeCache
27 if f not in self.cache:
28 self.cache[f] = os.stat(f)[stat.ST_MTIME]
29 return self.cache[f]
32 if f not in self.cache:
34 self.cache[f] = os.stat(f)[stat.ST_MTIME]
37 return self.cache[f]
40 self.cache[f] = os.stat(f)[stat.ST_MTIME]
41 return self.cache[f]
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