1*29075cc0SBryan Brattlof// SPDX-License-Identifier: GPL-2.0 2*29075cc0SBryan Brattlof/* 3*29075cc0SBryan Brattlof * Device Tree file for the AM62P5 SoC family (quad core) 4*29075cc0SBryan Brattlof * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 5*29075cc0SBryan Brattlof * 6*29075cc0SBryan Brattlof * TRM: https://www.ti.com/lit/pdf/spruj83 7*29075cc0SBryan Brattlof */ 8*29075cc0SBryan Brattlof 9*29075cc0SBryan Brattlof/dts-v1/; 10*29075cc0SBryan Brattlof 11*29075cc0SBryan Brattlof#include "k3-am62p.dtsi" 12*29075cc0SBryan Brattlof 13*29075cc0SBryan Brattlof/ { 14*29075cc0SBryan Brattlof cpus { 15*29075cc0SBryan Brattlof #address-cells = <1>; 16*29075cc0SBryan Brattlof #size-cells = <0>; 17*29075cc0SBryan Brattlof 18*29075cc0SBryan Brattlof cpu-map { 19*29075cc0SBryan Brattlof cluster0: cluster0 { 20*29075cc0SBryan Brattlof core0 { 21*29075cc0SBryan Brattlof cpu = <&cpu0>; 22*29075cc0SBryan Brattlof }; 23*29075cc0SBryan Brattlof 24*29075cc0SBryan Brattlof core1 { 25*29075cc0SBryan Brattlof cpu = <&cpu1>; 26*29075cc0SBryan Brattlof }; 27*29075cc0SBryan Brattlof 28*29075cc0SBryan Brattlof core2 { 29*29075cc0SBryan Brattlof cpu = <&cpu2>; 30*29075cc0SBryan Brattlof }; 31*29075cc0SBryan Brattlof 32*29075cc0SBryan Brattlof core3 { 33*29075cc0SBryan Brattlof cpu = <&cpu3>; 34*29075cc0SBryan Brattlof }; 35*29075cc0SBryan Brattlof }; 36*29075cc0SBryan Brattlof }; 37*29075cc0SBryan Brattlof 38*29075cc0SBryan Brattlof cpu0: cpu@0 { 39*29075cc0SBryan Brattlof compatible = "arm,cortex-a53"; 40*29075cc0SBryan Brattlof reg = <0x000>; 41*29075cc0SBryan Brattlof device_type = "cpu"; 42*29075cc0SBryan Brattlof enable-method = "psci"; 43*29075cc0SBryan Brattlof i-cache-size = <0x8000>; 44*29075cc0SBryan Brattlof i-cache-line-size = <64>; 45*29075cc0SBryan Brattlof i-cache-sets = <256>; 46*29075cc0SBryan Brattlof d-cache-size = <0x8000>; 47*29075cc0SBryan Brattlof d-cache-line-size = <64>; 48*29075cc0SBryan Brattlof d-cache-sets = <128>; 49*29075cc0SBryan Brattlof next-level-cache = <&l2_0>; 50*29075cc0SBryan Brattlof clocks = <&k3_clks 135 0>; 51*29075cc0SBryan Brattlof }; 52*29075cc0SBryan Brattlof 53*29075cc0SBryan Brattlof cpu1: cpu@1 { 54*29075cc0SBryan Brattlof compatible = "arm,cortex-a53"; 55*29075cc0SBryan Brattlof reg = <0x001>; 56*29075cc0SBryan Brattlof device_type = "cpu"; 57*29075cc0SBryan Brattlof enable-method = "psci"; 58*29075cc0SBryan Brattlof i-cache-size = <0x8000>; 59*29075cc0SBryan Brattlof i-cache-line-size = <64>; 60*29075cc0SBryan Brattlof i-cache-sets = <256>; 61*29075cc0SBryan Brattlof d-cache-size = <0x8000>; 62*29075cc0SBryan Brattlof d-cache-line-size = <64>; 63*29075cc0SBryan Brattlof d-cache-sets = <128>; 64*29075cc0SBryan Brattlof next-level-cache = <&l2_0>; 65*29075cc0SBryan Brattlof clocks = <&k3_clks 136 0>; 66*29075cc0SBryan Brattlof }; 67*29075cc0SBryan Brattlof 68*29075cc0SBryan Brattlof cpu2: cpu@2 { 69*29075cc0SBryan Brattlof compatible = "arm,cortex-a53"; 70*29075cc0SBryan Brattlof reg = <0x002>; 71*29075cc0SBryan Brattlof device_type = "cpu"; 72*29075cc0SBryan Brattlof enable-method = "psci"; 73*29075cc0SBryan Brattlof i-cache-size = <0x8000>; 74*29075cc0SBryan Brattlof i-cache-line-size = <64>; 75*29075cc0SBryan Brattlof i-cache-sets = <256>; 76*29075cc0SBryan Brattlof d-cache-size = <0x8000>; 77*29075cc0SBryan Brattlof d-cache-line-size = <64>; 78*29075cc0SBryan Brattlof d-cache-sets = <128>; 79*29075cc0SBryan Brattlof next-level-cache = <&l2_0>; 80*29075cc0SBryan Brattlof clocks = <&k3_clks 137 0>; 81*29075cc0SBryan Brattlof }; 82*29075cc0SBryan Brattlof 83*29075cc0SBryan Brattlof cpu3: cpu@3 { 84*29075cc0SBryan Brattlof compatible = "arm,cortex-a53"; 85*29075cc0SBryan Brattlof reg = <0x003>; 86*29075cc0SBryan Brattlof device_type = "cpu"; 87*29075cc0SBryan Brattlof enable-method = "psci"; 88*29075cc0SBryan Brattlof i-cache-size = <0x8000>; 89*29075cc0SBryan Brattlof i-cache-line-size = <64>; 90*29075cc0SBryan Brattlof i-cache-sets = <256>; 91*29075cc0SBryan Brattlof d-cache-size = <0x8000>; 92*29075cc0SBryan Brattlof d-cache-line-size = <64>; 93*29075cc0SBryan Brattlof d-cache-sets = <128>; 94*29075cc0SBryan Brattlof next-level-cache = <&l2_0>; 95*29075cc0SBryan Brattlof clocks = <&k3_clks 138 0>; 96*29075cc0SBryan Brattlof }; 97*29075cc0SBryan Brattlof }; 98*29075cc0SBryan Brattlof 99*29075cc0SBryan Brattlof l2_0: l2-cache0 { 100*29075cc0SBryan Brattlof compatible = "cache"; 101*29075cc0SBryan Brattlof cache-unified; 102*29075cc0SBryan Brattlof cache-level = <2>; 103*29075cc0SBryan Brattlof cache-size = <0x80000>; 104*29075cc0SBryan Brattlof cache-line-size = <64>; 105*29075cc0SBryan Brattlof cache-sets = <512>; 106*29075cc0SBryan Brattlof }; 107*29075cc0SBryan Brattlof}; 108