| /openbmc/u-boot/drivers/mmc/ |
| H A D | s5p_sdhci.c | 97 if (host->bus_width == 8) in s5p_sdhci_core_init()
107 int s5p_sdhci_init(u32 regbase, int index, int bus_width) in s5p_sdhci_init() argument
116 host->bus_width = bus_width; in s5p_sdhci_init()
125 flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; in do_sdhci_init()
156 int bus_width, dev_id; in sdhci_get_config() local
168 bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0); in sdhci_get_config()
169 if (bus_width <= 0) { in sdhci_get_config()
173 host->bus_width = bus_width; in sdhci_get_config()
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| H A D | arm_pl180_mmci.c | 317 if (dev->bus_width) { in host_set_ios()
320 switch (dev->bus_width) { in host_set_ios()
331 printf("Invalid bus width: %d\n", dev->bus_width); in host_set_ios()
424 u32 bus_width; in arm_pl180_mmc_probe() local
453 bus_width = dev_read_u32_default(dev, "bus-width", 1); in arm_pl180_mmc_probe()
454 switch (bus_width) { in arm_pl180_mmc_probe()
464 dev_err(dev, "Invalid bus-width value %u\n", bus_width); in arm_pl180_mmc_probe()
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| H A D | tegra_mmc.c | 418 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); in tegra_mmc_set_ios()
433 if (mmc->bus_width == 8) in tegra_mmc_set_ios()
435 else if (mmc->bus_width == 4) in tegra_mmc_set_ios()
595 int bus_width, ret; in tegra_mmc_probe() local
599 bus_width = dev_read_u32_default(dev, "bus-width", 1); in tegra_mmc_probe()
603 if (bus_width == 8) in tegra_mmc_probe()
605 if (bus_width >= 4) in tegra_mmc_probe()
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| H A D | rockchip_sdhci.c | 68 if (host->bus_width == 8) in arasan_sdhci_probe()
90 host->bus_width = dev_read_u32_default(dev, "bus-width", 4); in arasan_sdhci_ofdata_to_platdata()
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| H A D | sunxi_mmc.c | 273 mmc->bus_width, mmc->clock); in sunxi_mmc_set_ios_common()
282 if (mmc->bus_width == 8) in sunxi_mmc_set_ios_common()
284 else if (mmc->bus_width == 4) in sunxi_mmc_set_ios_common()
616 int bus_width, ret; in sunxi_mmc_probe() local
619 bus_width = dev_read_u32_default(dev, "bus-width", 1); in sunxi_mmc_probe()
623 if (bus_width == 8) in sunxi_mmc_probe()
625 if (bus_width >= 4) in sunxi_mmc_probe()
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| H A D | aspeed_sdhci.c | 88 host->bus_width = dev_read_u32_default(dev, "bus-width", 4); in aspeed_sdhci_probe()
90 if (host->bus_width == 8) in aspeed_sdhci_probe()
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| H A D | fsl_esdhc.c | 128 unsigned int bus_width; member
903 if (mmc->bus_width == 8) in fsl_esdhc_execute_tuning()
905 else if (mmc->bus_width == 4) in fsl_esdhc_execute_tuning()
997 if (mmc->bus_width == 4) in esdhc_set_ios_common()
999 else if (mmc->bus_width == 8) in esdhc_set_ios_common()
1237 if (priv->bus_width == 8) in fsl_esdhc_init()
1239 else if (priv->bus_width == 4) in fsl_esdhc_init()
1247 if (priv->bus_width > 0) { in fsl_esdhc_init()
1248 if (priv->bus_width < 8) in fsl_esdhc_init()
1250 if (priv->bus_width < 4) in fsl_esdhc_init()
[all …]
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| H A D | sh_mmcif.c | 364 switch (host->bus_width) { in sh_mmcif_set_cmd()
549 if (mmc->bus_width == 8) in sh_mmcif_set_ios_common()
550 host->bus_width = MMC_BUS_WIDTH_8; in sh_mmcif_set_ios_common()
551 else if (mmc->bus_width == 4) in sh_mmcif_set_ios_common()
552 host->bus_width = MMC_BUS_WIDTH_4; in sh_mmcif_set_ios_common()
554 host->bus_width = MMC_BUS_WIDTH_1; in sh_mmcif_set_ios_common()
556 debug("clock = %d, buswidth = %d\n", mmc->clock, mmc->bus_width); in sh_mmcif_set_ios_common()
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| H A D | meson_gx_mmc.c | 73 if (mmc->bus_width == 1) in meson_dm_mmc_set_ios()
75 else if (mmc->bus_width == 4) in meson_dm_mmc_set_ios()
77 else if (mmc->bus_width == 8) in meson_dm_mmc_set_ios()
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| /openbmc/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | mv_ddr_topology.c | 75 iface_params->bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data); in mv_ddr_topology_map_update()
174 unsigned int bus_width; in mv_ddr_if_bus_width_get() local
180 bus_width = 16; in mv_ddr_if_bus_width_get()
185 bus_width = 32; in mv_ddr_if_bus_width_get()
189 bus_width = 64; in mv_ddr_if_bus_width_get()
193 bus_width = 0; in mv_ddr_if_bus_width_get()
196 return bus_width; in mv_ddr_if_bus_width_get()
257 if (iface_params->bus_width == MV_DDR_DEV_WIDTH_8BIT) in mv_ddr_mem_sz_per_cs_get()
259 else if (iface_params->bus_width == MV_DDR_DEV_WIDTH_16BIT) in mv_ddr_mem_sz_per_cs_get()
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| H A D | mv_ddr_training_db.h | 35 u32 mv_ddr_page_size_get(enum mv_ddr_dev_width bus_width, enum mv_ddr_die_capacity mem_size);
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| /openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
| H A D | mmc.h | 55 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
57 static inline int s5p_mmc_init(int index, int bus_width) in s5p_mmc_init() argument
62 return s5p_sdhci_init(base, index, bus_width); in s5p_mmc_init()
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| /openbmc/u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | mmc.h | 57 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
59 static inline int s5p_mmc_init(int index, int bus_width) in s5p_mmc_init() argument
64 return s5p_sdhci_init(base, index, bus_width); in s5p_mmc_init()
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| /openbmc/u-boot/drivers/video/ |
| H A D | mxsfb.c | 53 uint32_t word_len = 0, bus_width = 0; in mxs_lcd_init() local
65 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT; in mxs_lcd_init()
70 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT; in mxs_lcd_init()
75 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT; in mxs_lcd_init()
80 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT; in mxs_lcd_init()
85 writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE | in mxs_lcd_init()
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun6i.c | 22 u8 bus_width; member
64 if (para->bus_width == 32) { in mctl_dll_init()
74 if (para->bus_width == 32) { in mctl_dll_init()
84 if (para->bus_width == 32) { in mctl_dll_init()
182 para->bus_width = 16; in mctl_channel_init()
243 if (para->bus_width == 16) in mctl_channel_init()
272 ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) | in mctl_com_init()
337 .bus_width = 32, in sunxi_dram_init()
383 bus = (para.bus_width == 32) ? 2 : 1; in sunxi_dram_init()
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| H A D | dram_sun8i_a33.c | 28 u8 bus_width; member
40 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | in mctl_set_cr()
233 para->bus_width = 16; in mctl_channel_init()
276 para->bus_width = 8; in mctl_channel_init()
339 .bus_width = 16, in sunxi_dram_init()
359 return para.page_size * (para.bus_width / 8) * in sunxi_dram_init()
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| H A D | dram_sun8i_a23.c | 90 static void mctl_init(u32 *bus_width) in mctl_init() argument
244 *bus_width = 8; in mctl_init()
251 *bus_width = 16; in mctl_init()
271 u32 bus, bus_width, offset, page_size, rows; in sunxi_dram_init() local
274 mctl_init(&bus_width); in sunxi_dram_init()
276 if (bus_width == 16) { in sunxi_dram_init()
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| H A D | dram_sun8i_a83t.c | 26 u8 bus_width; member
39 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | in mctl_set_cr()
316 para->bus_width = 16; in mctl_channel_init()
368 para->bus_width = 8; in mctl_channel_init()
416 para->bus_width = 16; in mctl_sys_init()
437 .bus_width = 16, in sunxi_dram_init()
469 return para.page_size * (para.bus_width / 8) * in sunxi_dram_init()
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| /openbmc/u-boot/drivers/ddr/fsl/ |
| H A D | ddr3_dimm_params.c | 63 if ((spd->bus_width & 0x7) < 4) in compute_ranksize()
64 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; in compute_ranksize()
122 pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); in ddr_compute_dimm_parameters()
123 if ((spd->bus_width >> 3) & 0x3) in ddr_compute_dimm_parameters()
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| H A D | ddr4_dimm_params.c | 98 if ((spd->bus_width & 0x7) < 4) in compute_ranksize()
99 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3; in compute_ranksize()
174 pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7)); in ddr_compute_dimm_parameters()
175 if ((spd->bus_width >> 3) & 0x3) in ddr_compute_dimm_parameters()
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| H A D | arm_ddr_gen3.c | 33 unsigned int i, bus_width; in fsl_ddr_set_memctl_regs() local
222 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) in fsl_ddr_set_memctl_regs()
224 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / in fsl_ddr_set_memctl_regs()
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| /openbmc/u-boot/arch/arm/include/asm/arch-hi6220/ |
| H A D | dwmmc.h | 7 int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
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| /openbmc/u-boot/board/sunxi/ |
| H A D | dram_sun4i_auto.c | 10 .bus_width = 0,
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| H A D | dram_sun5i_auto.c | 13 .bus_width = 0,
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| /openbmc/qemu/include/hw/dma/ |
| H A D | xlnx-zdma.h | 63 uint32_t bus_width; member
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