1*ebb1a593SChris Packham /* SPDX-License-Identifier: GPL-2.0 */ 2*ebb1a593SChris Packham /* 3*ebb1a593SChris Packham * Copyright (C) 2018 Marvell International Ltd. 4*ebb1a593SChris Packham */ 5*ebb1a593SChris Packham 6*ebb1a593SChris Packham #ifndef _MV_DDR_TRAINING_DB_H 7*ebb1a593SChris Packham #define _MV_DDR_TRAINING_DB_H 8*ebb1a593SChris Packham 9*ebb1a593SChris Packham #include "mv_ddr_topology.h" 10*ebb1a593SChris Packham 11*ebb1a593SChris Packham /* in ns */ 12*ebb1a593SChris Packham #define TREFI_LOW 7800 13*ebb1a593SChris Packham #define TREFI_HIGH 3900 14*ebb1a593SChris Packham 15*ebb1a593SChris Packham enum mv_ddr_page_size { 16*ebb1a593SChris Packham MV_DDR_PAGE_SIZE_1K = 1, 17*ebb1a593SChris Packham MV_DDR_PAGE_SIZE_2K 18*ebb1a593SChris Packham }; 19*ebb1a593SChris Packham 20*ebb1a593SChris Packham struct mv_ddr_page_element { 21*ebb1a593SChris Packham /* 8-bit bus width page size */ 22*ebb1a593SChris Packham enum mv_ddr_page_size page_size_8bit; 23*ebb1a593SChris Packham /* 16-bit bus width page size */ 24*ebb1a593SChris Packham enum mv_ddr_page_size page_size_16bit; 25*ebb1a593SChris Packham }; 26*ebb1a593SChris Packham 27*ebb1a593SChris Packham /* cas latency value per frequency */ 28*ebb1a593SChris Packham struct mv_ddr_cl_val_per_freq { 29*ebb1a593SChris Packham unsigned int cl_val[MV_DDR_FREQ_LAST]; 30*ebb1a593SChris Packham }; 31*ebb1a593SChris Packham 32*ebb1a593SChris Packham u32 mv_ddr_rfc_get(u32 mem); 33*ebb1a593SChris Packham unsigned int *mv_ddr_freq_tbl_get(void); 34*ebb1a593SChris Packham u32 mv_ddr_freq_get(enum mv_ddr_freq freq); 35*ebb1a593SChris Packham u32 mv_ddr_page_size_get(enum mv_ddr_dev_width bus_width, enum mv_ddr_die_capacity mem_size); 36*ebb1a593SChris Packham unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_ddr_speed_bin_timing element); 37*ebb1a593SChris Packham u32 mv_ddr_cl_val_get(u32 index, u32 freq); 38*ebb1a593SChris Packham u32 mv_ddr_cwl_val_get(u32 index, u32 freq); 39*ebb1a593SChris Packham 40*ebb1a593SChris Packham #endif /* _MV_DDR_TRAINING_DB_H */ 41