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/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
30 # bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged
31 # bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged
[all …]
H A Dkwbimage_128M16_1.cfg20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
30 # bit 3-0: 0, MPPSel8 GPIO[8]
31 # bit 7-4: 0, MPPSel9 GPIO[9]
[all …]
/openbmc/u-boot/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
82 #define STM32F4_APB1_CLOCK(bit) (STM32F4_RCC_APB1_##bit + 0x80) argument
105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) argument
106 #define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) argument
H A Dstm32f7-rcc.h33 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8)) argument
34 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit) argument
44 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F7_AHB3_CLOCK(bit) (STM32F7_RCC_AHB3_##bit + 0x40) argument
85 #define STM32F7_APB1_RESET(bit) (STM32F7_RCC_APB1_##bit + (0x20 * 8)) argument
86 #define STM32F7_APB1_CLOCK(bit) (STM32F7_RCC_APB1_##bit + 0x80) argument
111 #define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8)) argument
112 #define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0) argument
H A Dstm32h7-rcc.h17 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8)) argument
29 #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8)) argument
38 #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8)) argument
57 #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8)) argument
64 #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit + (0x8C * 8)) argument
92 #define STM32H7_APB1L_RESET(bit) (STM32H7_RCC_APB1L_##bit + (0x90 * 8)) argument
101 #define STM32H7_APB1H_RESET(bit) (STM32H7_RCC_APB1H_##bit + (0x94 * 8)) argument
120 #define STM32H7_APB2_RESET(bit) (STM32H7_RCC_APB2_##bit + (0x98 * 8)) argument
136 #define STM32H7_APB4_RESET(bit) (STM32H7_RCC_APB4_##bit + (0x9C * 8)) argument
/openbmc/openbmc/poky/meta/classes-recipe/
H A Dsiteinfo.bbclass18 # * bits: Returns the bit size of the target, either "32" or "64"
26 …"allarch": "endian-little bit-32", # bogus, but better than special-casing the checks below for al…
27 "aarch64": "endian-little bit-64 arm-common arm-64",
28 "aarch64_be": "endian-big bit-64 arm-common arm-64",
29 "arc": "endian-little bit-32 arc-common",
30 "arceb": "endian-big bit-32 arc-common",
31 "arm": "endian-little bit-32 arm-common arm-32",
32 "armeb": "endian-big bit-32 arm-common arm-32",
33 "avr32": "endian-big bit-32 avr32-common",
34 "bfin": "endian-little bit-32 bfin-common",
[all …]
/openbmc/u-boot/arch/mips/
H A Dconfig.mk7 32bit-emul := elf32btsmip
8 64bit-emul := elf64btsmip
9 32bit-bfd := elf32-tradbigmips
10 64bit-bfd := elf64-tradbigmips
16 32bit-emul := elf32ltsmip
17 64bit-emul := elf64ltsmip
18 32bit-bfd := elf32-tradlittlemips
19 64bit-bfd := elf64-tradlittlemips
26 PLATFORM_LDFLAGS += -m $(32bit-emul)
27 OBJCOPYFLAGS += -O $(32bit-bfd)
[all …]
/openbmc/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rv1108.c19 .bit = 0,
25 .bit = 2,
31 .bit = 4,
37 .bit = 6,
43 .bit = 8,
49 .bit = 10,
55 .bit = 12,
61 .bit = 14,
67 .bit = 0,
73 .bit = 2,
[all …]
H A Dpinctrl-rk3368.c19 int *reg, u8 *bit) in rk3368_calc_pull_reg_and_bit() argument
29 *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; in rk3368_calc_pull_reg_and_bit()
30 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; in rk3368_calc_pull_reg_and_bit()
40 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); in rk3368_calc_pull_reg_and_bit()
41 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; in rk3368_calc_pull_reg_and_bit()
50 int *reg, u8 *bit) in rk3368_calc_drv_reg_and_bit() argument
60 *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG; in rk3368_calc_drv_reg_and_bit()
61 *bit *= ROCKCHIP_DRV_BITS_PER_PIN; in rk3368_calc_drv_reg_and_bit()
71 *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); in rk3368_calc_drv_reg_and_bit()
72 *bit *= ROCKCHIP_DRV_BITS_PER_PIN; in rk3368_calc_drv_reg_and_bit()
H A Dpinctrl-rk3288.c37 int *reg, u8 *bit) in rk3288_calc_pull_reg_and_bit() argument
47 *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG; in rk3288_calc_pull_reg_and_bit()
48 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; in rk3288_calc_pull_reg_and_bit()
58 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG); in rk3288_calc_pull_reg_and_bit()
59 *bit *= ROCKCHIP_PULL_BITS_PER_PIN; in rk3288_calc_pull_reg_and_bit()
68 int *reg, u8 *bit) in rk3288_calc_drv_reg_and_bit() argument
78 *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG; in rk3288_calc_drv_reg_and_bit()
79 *bit *= ROCKCHIP_DRV_BITS_PER_PIN; in rk3288_calc_drv_reg_and_bit()
89 *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG); in rk3288_calc_drv_reg_and_bit()
90 *bit *= ROCKCHIP_DRV_BITS_PER_PIN; in rk3288_calc_drv_reg_and_bit()
/openbmc/u-boot/drivers/pinctrl/meson/
H A Dpinctrl-meson.c58 unsigned int *reg, unsigned int *bit) in meson_gpio_calc_reg_and_bit() argument
81 *bit = desc->bit + pin - bank->first; in meson_gpio_calc_reg_and_bit()
89 unsigned int reg, bit; in meson_gpio_get() local
93 &bit); in meson_gpio_get()
97 return !!(readl(priv->reg_gpio + reg) & BIT(bit)); in meson_gpio_get()
103 unsigned int reg, bit; in meson_gpio_set() local
107 &bit); in meson_gpio_set()
111 clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0); in meson_gpio_set()
119 unsigned int reg, bit, val; in meson_gpio_get_direction() local
123 &bit); in meson_gpio_get_direction()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Domap3xxx-clocks.dtsi28 ti,bit-shift = <6>;
39 ti,bit-shift = <7>;
88 ti,bit-shift = <4>;
102 ti,bit-shift = <2>;
116 ti,bit-shift = <6>;
143 ti,bit-shift = <2>;
224 ti,bit-shift = <0x1b>;
226 ti,set-bit-to-disable;
248 ti,bit-shift = <16>;
266 ti,bit-shift = <0xc>;
[all …]
H A Ddra7xx-clocks.dtsi220 ti,invert-autoidle-bit;
240 ti,invert-autoidle-bit;
251 ti,invert-autoidle-bit;
258 ti,bit-shift = <23>;
283 ti,invert-autoidle-bit;
309 ti,invert-autoidle-bit;
332 ti,bit-shift = <23>;
353 ti,invert-autoidle-bit;
370 ti,bit-shift = <23>;
391 ti,invert-autoidle-bit;
[all …]
H A Domap34xx-omap36xx-clocks.dtsi23 ti,bit-shift = <3>;
32 ti,bit-shift = <2>;
40 ti,bit-shift = <1>;
48 ti,bit-shift = <0>;
55 ti,bit-shift = <0>;
65 ti,bit-shift = <0>;
73 ti,bit-shift = <1>;
89 ti,bit-shift = <4>;
97 ti,bit-shift = <29>;
105 ti,bit-shift = <26>;
[all …]
H A Domap36xx-clocks.dtsi22 ti,bit-shift = <0x1e>;
25 ti,set-bit-to-disable;
32 ti,bit-shift = <0x1b>;
34 ti,set-bit-to-disable;
41 ti,bit-shift = <0xc>;
43 ti,set-bit-to-disable;
50 ti,bit-shift = <0x1c>;
52 ti,set-bit-to-disable;
59 ti,bit-shift = <0x1f>;
61 ti,set-bit-to-disable;
[all …]
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_pbs.c48 u32 pup = 0, bit = 0, if_id = 0, all_lock = 0, cs_num = 0; in ddr3_tip_pbs() local
101 for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) { in ddr3_tip_pbs()
106 bit + pup * BUS_WIDTH_IN_BITS], in ddr3_tip_pbs()
113 if_id, bit, pup, in ddr3_tip_pbs()
132 if_id, bit, pup, in ddr3_tip_pbs()
219 for (bit = 0; bit < BUS_WIDTH_IN_BITS; bit++) { in ddr3_tip_pbs()
224 bit + pup * in ddr3_tip_pbs()
229 if_id, bit, pup, in ddr3_tip_pbs()
235 bit = BUS_WIDTH_IN_BITS; in ddr3_tip_pbs()
270 bit = BUS_WIDTH_IN_BITS; in ddr3_tip_pbs()
[all …]
/openbmc/qemu/target/s390x/
H A Dcpu_features.c25 .bit = _BIT, \
38 S390Feat s390_feat_by_type_and_bit(S390FeatType type, int bit) in s390_feat_by_type_and_bit() argument
44 s390_features[feat].bit == bit) { in s390_feat_by_type_and_bit()
106 bit_nr = s390_features[feat].bit; in s390_fill_feat_block()
129 clear_be_bit(s390_feat_def(S390_FEAT_SIE_F2)->bit, data); in s390_fill_feat_block()
130 clear_be_bit(s390_feat_def(S390_FEAT_SIE_SKEY)->bit, data); in s390_fill_feat_block()
131 clear_be_bit(s390_feat_def(S390_FEAT_SIE_GPERE)->bit, data); in s390_fill_feat_block()
132 clear_be_bit(s390_feat_def(S390_FEAT_SIE_SIIF)->bit, data); in s390_fill_feat_block()
133 clear_be_bit(s390_feat_def(S390_FEAT_SIE_SIGPIF)->bit, data); in s390_fill_feat_block()
134 clear_be_bit(s390_feat_def(S390_FEAT_SIE_IB)->bit, data); in s390_fill_feat_block()
[all …]
/openbmc/u-boot/arch/sandbox/
H A DKconfig14 bool "Use 64-bit addresses"
27 prompt "Run sandbox on 32/64-bit host"
30 Sandbox can be built on 32-bit and 64-bit hosts.
31 The default is to build on a 64-bit host and run
32 on a 64-bit host. If you want to run sandbox on
33 a 32-bit host, change it here.
36 bool "32-bit host"
40 bool "64-bit host"
/openbmc/u-boot/fs/yaffs2/
H A Dyaffs_ecc.c153 unsigned bit; in yaffs_ecc_correct() local
155 bit = byte = 0; in yaffs_ecc_correct()
175 bit |= 0x04; in yaffs_ecc_correct()
177 bit |= 0x02; in yaffs_ecc_correct()
179 bit |= 0x01; in yaffs_ecc_correct()
181 data[byte] ^= (1 << bit); in yaffs_ecc_correct()
238 unsigned bit; in yaffs_ecc_correct_other() local
252 bit = 0; in yaffs_ecc_correct_other()
255 bit |= 0x04; in yaffs_ecc_correct_other()
257 bit |= 0x02; in yaffs_ecc_correct_other()
[all …]
/openbmc/u-boot/drivers/gpio/
H A Ddb8500_gpio.c88 u32 bit = 1 << offset; in gpio_set_mode() local
91 afunc = readl(addr + DB8500_GPIO_AFSLA) & ~bit; in gpio_set_mode()
92 bfunc = readl(addr + DB8500_GPIO_AFSLB) & ~bit; in gpio_set_mode()
94 afunc |= bit; in gpio_set_mode()
96 bfunc |= bit; in gpio_set_mode()
119 u32 bit = 1 << offset; in db8500_gpio_set_pull() local
124 pdis |= bit; in db8500_gpio_set_pull()
126 pdis &= ~bit; in db8500_gpio_set_pull()
130 writel(bit, addr + DB8500_GPIO_DATS); in db8500_gpio_set_pull()
132 writel(bit, addr + DB8500_GPIO_DATC); in db8500_gpio_set_pull()
[all …]
/openbmc/qemu/ui/
H A Dcursor.c136 uint8_t bit; in cursor_set_mono() local
148 bit = 0x80; in cursor_set_mono()
150 if (transparent && mask[x/8] & bit) { in cursor_set_mono()
151 if (!expand_bitmap_only && image[x / 8] & bit) { in cursor_set_mono()
157 } else if (!transparent && !(mask[x/8] & bit)) { in cursor_set_mono()
159 } else if (image[x/8] & bit) { in cursor_set_mono()
164 bit >>= 1; in cursor_set_mono()
165 if (bit == 0) { in cursor_set_mono()
166 bit = 0x80; in cursor_set_mono()
203 uint8_t bit; in cursor_get_mono_mask() local
[all …]
/openbmc/qemu/configs/targets/
H A Driscv64-softmmu.mak4 …-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual…
/openbmc/qemu/docs/
H A Dxen-save-devices-state.txt19 32 bit big endian: QEMU_VM_FILE_MAGIC
20 32 bit big endian: QEMU_VM_FILE_VERSION
24 8 bit: QEMU_VM_SECTION_FULL
25 32 bit big endian: section_id
26 8 bit: idstr (ID string) length
28 32 bit big endian: instance_id
29 32 bit big endian: version_id
33 8 bit: QEMU_VM_EOF
/openbmc/openbmc/poky/meta/conf/distro/include/
H A Dtime64.inc13 # Only needed for some 32-bit architectures, some relatively newer
25 # both 32 and 64 bit file APIs. But it does not handle the time side?
33 INSANE_SKIP:append:pn-gcc-sanitizers = " 32bit-time"
34 INSANE_SKIP:append:pn-glibc = " 32bit-time"
36 # Strace has tests that call 32 bit API directly, which is fair enough, e.g.
37 # /usr/lib/strace/ptest/tests/ioctl_termios uses 32-bit api 'ioctl'
38 INSANE_SKIP:append:pn-strace = " 32bit-time"
40 # Pseudo has to wrap all glibc calls including the 32 bit ones even
42 INSANE_SKIP:append:pn-pseudo = " 32bit-time"
50 …x86_64-oesdk-linux/usr/bin/arm-oe-linux-gnueabi/arm-oe-linux-gnueabi-ranlib uses 32-bit api 'lstat'
[all …]
/openbmc/u-boot/doc/device-tree-bindings/timer/
H A Datcpit100_timer.txt11 One 32-bit timer
12 Two 16-bit timers
13 Four 8-bit timers
14 One 16-bit PWM
15 One 16-bit timer and one 8-bit PWM
16 Two 8-bit timer and one 8-bit PWM

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