1e7ae4cf2SDavid Wu // SPDX-License-Identifier: GPL-2.0+
2e7ae4cf2SDavid Wu /*
3e7ae4cf2SDavid Wu * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4e7ae4cf2SDavid Wu */
5e7ae4cf2SDavid Wu
6e7ae4cf2SDavid Wu #include <common.h>
7e7ae4cf2SDavid Wu #include <dm.h>
8e7ae4cf2SDavid Wu #include <dm/pinctrl.h>
9e7ae4cf2SDavid Wu #include <regmap.h>
10e7ae4cf2SDavid Wu #include <syscon.h>
11e7ae4cf2SDavid Wu
12e7ae4cf2SDavid Wu #include "pinctrl-rockchip.h"
13e7ae4cf2SDavid Wu
14e7ae4cf2SDavid Wu static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
15e7ae4cf2SDavid Wu {
16e7ae4cf2SDavid Wu /* edphdmi_cecinoutt1 */
17e7ae4cf2SDavid Wu .bank_num = 7,
18e7ae4cf2SDavid Wu .pin = 16,
19e7ae4cf2SDavid Wu .func = 2,
20e7ae4cf2SDavid Wu .route_offset = 0x264,
21e7ae4cf2SDavid Wu .route_val = BIT(16 + 12) | BIT(12),
22e7ae4cf2SDavid Wu }, {
23e7ae4cf2SDavid Wu /* edphdmi_cecinout */
24e7ae4cf2SDavid Wu .bank_num = 7,
25e7ae4cf2SDavid Wu .pin = 23,
26e7ae4cf2SDavid Wu .func = 4,
27e7ae4cf2SDavid Wu .route_offset = 0x264,
28e7ae4cf2SDavid Wu .route_val = BIT(16 + 12),
29e7ae4cf2SDavid Wu },
30e7ae4cf2SDavid Wu };
31e7ae4cf2SDavid Wu
32e7ae4cf2SDavid Wu #define RK3288_PULL_OFFSET 0x140
33e7ae4cf2SDavid Wu #define RK3288_PULL_PMU_OFFSET 0x64
34e7ae4cf2SDavid Wu
rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)35e7ae4cf2SDavid Wu static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
36e7ae4cf2SDavid Wu int pin_num, struct regmap **regmap,
37e7ae4cf2SDavid Wu int *reg, u8 *bit)
38e7ae4cf2SDavid Wu {
39e7ae4cf2SDavid Wu struct rockchip_pinctrl_priv *priv = bank->priv;
40e7ae4cf2SDavid Wu
41e7ae4cf2SDavid Wu /* The first 24 pins of the first bank are located in PMU */
42e7ae4cf2SDavid Wu if (bank->bank_num == 0) {
43e7ae4cf2SDavid Wu *regmap = priv->regmap_pmu;
44e7ae4cf2SDavid Wu *reg = RK3288_PULL_PMU_OFFSET;
45e7ae4cf2SDavid Wu
46e7ae4cf2SDavid Wu *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
47e7ae4cf2SDavid Wu *bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
48e7ae4cf2SDavid Wu *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
49e7ae4cf2SDavid Wu } else {
50e7ae4cf2SDavid Wu *regmap = priv->regmap_base;
51e7ae4cf2SDavid Wu *reg = RK3288_PULL_OFFSET;
52e7ae4cf2SDavid Wu
53e7ae4cf2SDavid Wu /* correct the offset, as we're starting with the 2nd bank */
54e7ae4cf2SDavid Wu *reg -= 0x10;
55e7ae4cf2SDavid Wu *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
56e7ae4cf2SDavid Wu *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
57e7ae4cf2SDavid Wu
58e7ae4cf2SDavid Wu *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
59e7ae4cf2SDavid Wu *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
60e7ae4cf2SDavid Wu }
61e7ae4cf2SDavid Wu }
62e7ae4cf2SDavid Wu
63e7ae4cf2SDavid Wu #define RK3288_DRV_PMU_OFFSET 0x70
64e7ae4cf2SDavid Wu #define RK3288_DRV_GRF_OFFSET 0x1c0
65e7ae4cf2SDavid Wu
rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)66e7ae4cf2SDavid Wu static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
67e7ae4cf2SDavid Wu int pin_num, struct regmap **regmap,
68e7ae4cf2SDavid Wu int *reg, u8 *bit)
69e7ae4cf2SDavid Wu {
70e7ae4cf2SDavid Wu struct rockchip_pinctrl_priv *priv = bank->priv;
71e7ae4cf2SDavid Wu
72e7ae4cf2SDavid Wu /* The first 24 pins of the first bank are located in PMU */
73e7ae4cf2SDavid Wu if (bank->bank_num == 0) {
74e7ae4cf2SDavid Wu *regmap = priv->regmap_pmu;
75e7ae4cf2SDavid Wu *reg = RK3288_DRV_PMU_OFFSET;
76e7ae4cf2SDavid Wu
77e7ae4cf2SDavid Wu *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
78e7ae4cf2SDavid Wu *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG;
79e7ae4cf2SDavid Wu *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
80e7ae4cf2SDavid Wu } else {
81e7ae4cf2SDavid Wu *regmap = priv->regmap_base;
82e7ae4cf2SDavid Wu *reg = RK3288_DRV_GRF_OFFSET;
83e7ae4cf2SDavid Wu
84e7ae4cf2SDavid Wu /* correct the offset, as we're starting with the 2nd bank */
85e7ae4cf2SDavid Wu *reg -= 0x10;
86e7ae4cf2SDavid Wu *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
87e7ae4cf2SDavid Wu *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
88e7ae4cf2SDavid Wu
89e7ae4cf2SDavid Wu *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
90e7ae4cf2SDavid Wu *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
91e7ae4cf2SDavid Wu }
92e7ae4cf2SDavid Wu }
93e7ae4cf2SDavid Wu
94e7ae4cf2SDavid Wu static struct rockchip_pin_bank rk3288_pin_banks[] = {
95*50298091SDavid Wu PIN_BANK_IOMUX_DRV_PULL_FLAGS(0, 24, "gpio0",
96*50298091SDavid Wu IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
97*50298091SDavid Wu IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
98*50298091SDavid Wu IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
99*50298091SDavid Wu IOMUX_UNROUTED,
100*50298091SDavid Wu DRV_TYPE_WRITABLE_32BIT,
101*50298091SDavid Wu DRV_TYPE_WRITABLE_32BIT,
102*50298091SDavid Wu DRV_TYPE_WRITABLE_32BIT,
103*50298091SDavid Wu 0,
104*50298091SDavid Wu PULL_TYPE_WRITABLE_32BIT,
105*50298091SDavid Wu PULL_TYPE_WRITABLE_32BIT,
106*50298091SDavid Wu PULL_TYPE_WRITABLE_32BIT,
107*50298091SDavid Wu 0
108e7ae4cf2SDavid Wu ),
109e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
110e7ae4cf2SDavid Wu IOMUX_UNROUTED,
111e7ae4cf2SDavid Wu IOMUX_UNROUTED,
112e7ae4cf2SDavid Wu 0
113e7ae4cf2SDavid Wu ),
114e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
115e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
116e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
117e7ae4cf2SDavid Wu IOMUX_WIDTH_4BIT,
118e7ae4cf2SDavid Wu 0,
119e7ae4cf2SDavid Wu 0
120e7ae4cf2SDavid Wu ),
121e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
122e7ae4cf2SDavid Wu 0,
123e7ae4cf2SDavid Wu 0,
124e7ae4cf2SDavid Wu IOMUX_UNROUTED
125e7ae4cf2SDavid Wu ),
126e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
127e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
128e7ae4cf2SDavid Wu 0,
129e7ae4cf2SDavid Wu IOMUX_WIDTH_4BIT,
130e7ae4cf2SDavid Wu IOMUX_UNROUTED
131e7ae4cf2SDavid Wu ),
132e7ae4cf2SDavid Wu PIN_BANK(8, 16, "gpio8"),
133e7ae4cf2SDavid Wu };
134e7ae4cf2SDavid Wu
135e7ae4cf2SDavid Wu static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
136e7ae4cf2SDavid Wu .pin_banks = rk3288_pin_banks,
137e7ae4cf2SDavid Wu .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
138e7ae4cf2SDavid Wu .label = "RK3288-GPIO",
139e7ae4cf2SDavid Wu .type = RK3288,
140e7ae4cf2SDavid Wu .grf_mux_offset = 0x0,
141e7ae4cf2SDavid Wu .pmu_mux_offset = 0x84,
142e7ae4cf2SDavid Wu .iomux_routes = rk3288_mux_route_data,
143e7ae4cf2SDavid Wu .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
144e7ae4cf2SDavid Wu .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
145e7ae4cf2SDavid Wu .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
146e7ae4cf2SDavid Wu };
147e7ae4cf2SDavid Wu
148e7ae4cf2SDavid Wu static const struct udevice_id rk3288_pinctrl_ids[] = {
149e7ae4cf2SDavid Wu {
150e7ae4cf2SDavid Wu .compatible = "rockchip,rk3288-pinctrl",
151e7ae4cf2SDavid Wu .data = (ulong)&rk3288_pin_ctrl
152e7ae4cf2SDavid Wu },
153e7ae4cf2SDavid Wu { }
154e7ae4cf2SDavid Wu };
155e7ae4cf2SDavid Wu
156e7ae4cf2SDavid Wu U_BOOT_DRIVER(pinctrl_rk3288) = {
157e7ae4cf2SDavid Wu .name = "rockchip_rk3288_pinctrl",
158e7ae4cf2SDavid Wu .id = UCLASS_PINCTRL,
159e7ae4cf2SDavid Wu .of_match = rk3288_pinctrl_ids,
160e7ae4cf2SDavid Wu .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
161e7ae4cf2SDavid Wu .ops = &rockchip_pinctrl_ops,
162e7ae4cf2SDavid Wu #if !CONFIG_IS_ENABLED(OF_PLATDATA)
163e7ae4cf2SDavid Wu .bind = dm_scan_fdt_dev,
164e7ae4cf2SDavid Wu #endif
165e7ae4cf2SDavid Wu .probe = rockchip_pinctrl_probe,
166e7ae4cf2SDavid Wu };
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