1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <dm/pinctrl.h>
9 #include <regmap.h>
10 #include <syscon.h>
11
12 #include "pinctrl-rockchip.h"
13
14 static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
15 {
16 .num = 1,
17 .pin = 0,
18 .reg = 0x418,
19 .bit = 0,
20 .mask = 0x3
21 }, {
22 .num = 1,
23 .pin = 1,
24 .reg = 0x418,
25 .bit = 2,
26 .mask = 0x3
27 }, {
28 .num = 1,
29 .pin = 2,
30 .reg = 0x418,
31 .bit = 4,
32 .mask = 0x3
33 }, {
34 .num = 1,
35 .pin = 3,
36 .reg = 0x418,
37 .bit = 6,
38 .mask = 0x3
39 }, {
40 .num = 1,
41 .pin = 4,
42 .reg = 0x418,
43 .bit = 8,
44 .mask = 0x3
45 }, {
46 .num = 1,
47 .pin = 5,
48 .reg = 0x418,
49 .bit = 10,
50 .mask = 0x3
51 }, {
52 .num = 1,
53 .pin = 6,
54 .reg = 0x418,
55 .bit = 12,
56 .mask = 0x3
57 }, {
58 .num = 1,
59 .pin = 7,
60 .reg = 0x418,
61 .bit = 14,
62 .mask = 0x3
63 }, {
64 .num = 1,
65 .pin = 8,
66 .reg = 0x41c,
67 .bit = 0,
68 .mask = 0x3
69 }, {
70 .num = 1,
71 .pin = 9,
72 .reg = 0x41c,
73 .bit = 2,
74 .mask = 0x3
75 },
76 };
77
78 #define RV1108_PULL_PMU_OFFSET 0x10
79 #define RV1108_PULL_OFFSET 0x110
80
rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)81 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
82 int pin_num, struct regmap **regmap,
83 int *reg, u8 *bit)
84 {
85 struct rockchip_pinctrl_priv *priv = bank->priv;
86
87 /* The first 24 pins of the first bank are located in PMU */
88 if (bank->bank_num == 0) {
89 *regmap = priv->regmap_pmu;
90 *reg = RV1108_PULL_PMU_OFFSET;
91 } else {
92 *reg = RV1108_PULL_OFFSET;
93 *regmap = priv->regmap_base;
94 /* correct the offset, as we're starting with the 2nd bank */
95 *reg -= 0x10;
96 *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
97 }
98
99 *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
100 *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
101 *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
102 }
103
104 #define RV1108_DRV_PMU_OFFSET 0x20
105 #define RV1108_DRV_GRF_OFFSET 0x210
106
rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)107 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
108 int pin_num, struct regmap **regmap,
109 int *reg, u8 *bit)
110 {
111 struct rockchip_pinctrl_priv *priv = bank->priv;
112
113 /* The first 24 pins of the first bank are located in PMU */
114 if (bank->bank_num == 0) {
115 *regmap = priv->regmap_pmu;
116 *reg = RV1108_DRV_PMU_OFFSET;
117 } else {
118 *regmap = priv->regmap_base;
119 *reg = RV1108_DRV_GRF_OFFSET;
120
121 /* correct the offset, as we're starting with the 2nd bank */
122 *reg -= 0x10;
123 *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
124 }
125
126 *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
127 *bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG;
128 *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
129 }
130
131 #define RV1108_SCHMITT_PMU_OFFSET 0x30
132 #define RV1108_SCHMITT_GRF_OFFSET 0x388
133 #define RV1108_SCHMITT_BANK_STRIDE 8
134 #define RV1108_SCHMITT_PINS_PER_GRF_REG 16
135 #define RV1108_SCHMITT_PINS_PER_PMU_REG 8
136
rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)137 static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
138 int pin_num,
139 struct regmap **regmap,
140 int *reg, u8 *bit)
141 {
142 struct rockchip_pinctrl_priv *priv = bank->priv;
143 int pins_per_reg;
144
145 if (bank->bank_num == 0) {
146 *regmap = priv->regmap_pmu;
147 *reg = RV1108_SCHMITT_PMU_OFFSET;
148 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
149 } else {
150 *regmap = priv->regmap_base;
151 *reg = RV1108_SCHMITT_GRF_OFFSET;
152 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
153 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
154 }
155 *reg += ((pin_num / pins_per_reg) * 4);
156 *bit = pin_num % pins_per_reg;
157
158 return 0;
159 }
160
161 static struct rockchip_pin_bank rv1108_pin_banks[] = {
162 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
163 IOMUX_SOURCE_PMU,
164 IOMUX_SOURCE_PMU,
165 IOMUX_SOURCE_PMU),
166 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
167 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
168 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
169 };
170
171 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
172 .pin_banks = rv1108_pin_banks,
173 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
174 .label = "RV1108-GPIO",
175 .type = RV1108,
176 .grf_mux_offset = 0x10,
177 .pmu_mux_offset = 0x0,
178 .iomux_recalced = rv1108_mux_recalced_data,
179 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
180 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
181 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
182 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
183 };
184
185 static const struct udevice_id rv1108_pinctrl_ids[] = {
186 {
187 .compatible = "rockchip,rv1108-pinctrl",
188 .data = (ulong)&rv1108_pin_ctrl
189 },
190 { }
191 };
192
193 U_BOOT_DRIVER(pinctrl_rv1108) = {
194 .name = "pinctrl_rv1108",
195 .id = UCLASS_PINCTRL,
196 .of_match = rv1108_pinctrl_ids,
197 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
198 .ops = &rockchip_pinctrl_ops,
199 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
200 .bind = dm_scan_fdt_dev,
201 #endif
202 .probe = rockchip_pinctrl_probe,
203 };
204