| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_device.c | 415 ret = adev->pcie_rreg(adev, reg * 4); in amdgpu_device_rreg()
499 adev->pcie_wreg(adev, reg * 4, v); in amdgpu_device_wreg()
527 adev->pcie_wreg(adev, reg * 4, v); in amdgpu_mm_wreg_mmio_rlc()
755 return adev->nbio.funcs->get_rev_id(adev); in amdgpu_device_get_rev_id()
1040 &adev->wb.wb_obj, &adev->wb.gpu_addr, in amdgpu_device_wb_init()
2488 if (memcmp(adev->gart.ptr, adev->reset_magic, in amdgpu_device_check_vram_lost()
2612 adev = gpu_ins->adev; in amdgpu_device_enable_mgpu_fan_boost()
3393 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; in amdgpu_device_get_job_timeout_settings()
3440 adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout; in amdgpu_device_get_job_timeout_settings()
3629 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); in amdgpu_device_init()
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| H A D | gmc_v10_0.c | 334 adev->hdp.funcs->flush_hdp(adev, NULL); in gmc_v10_0_flush_gpu_tlb()
524 struct amdgpu_device *adev = ring->adev; in gmc_v10_0_emit_pasid_mapping() local
819 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev); in gmc_v10_0_mc_init()
874 adev->gfxhub.funcs->init(adev); in gmc_v10_0_sw_init()
876 adev->mmhub.funcs->init(adev); in gmc_v10_0_sw_init()
1059 r = adev->mmhub.funcs->gart_enable(adev); in gmc_v10_0_gart_enable()
1063 adev->hdp.funcs->init_registers(adev); in gmc_v10_0_gart_enable()
1066 adev->hdp.funcs->flush_hdp(adev, NULL); in gmc_v10_0_gart_enable()
1111 adev->umc.funcs->init_registers(adev); in gmc_v10_0_hw_init()
1126 adev->gfxhub.funcs->gart_disable(adev); in gmc_v10_0_gart_disable()
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| H A D | gmc_v9_0.c | 1037 struct amdgpu_device *adev = ring->adev; in gmc_v9_0_emit_flush_gpu_tlb() local
1085 struct amdgpu_device *adev = ring->adev; in gmc_v9_0_emit_pasid_mapping() local
1595 adev->smuio.funcs->get_pkg_type(adev); in gmc_v9_0_early_init()
2020 adev->gfxhub.funcs->init(adev); in gmc_v9_0_sw_init()
2022 adev->mmhub.funcs->init(adev); in gmc_v9_0_sw_init()
2312 r = adev->mmhub.funcs->gart_enable(adev); in gmc_v9_0_gart_enable()
2346 adev->hdp.funcs->init_registers(adev); in gmc_v9_0_hw_init()
2349 adev->hdp.funcs->flush_hdp(adev, NULL); in gmc_v9_0_hw_init()
2368 adev->umc.funcs->init_registers(adev); in gmc_v9_0_hw_init()
2390 adev->gfxhub.funcs->gart_disable(adev); in gmc_v9_0_gart_disable()
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| H A D | gmc_v11_0.c | 292 adev->hdp.funcs->flush_hdp(adev, NULL); in gmc_v11_0_flush_gpu_tlb()
432 struct amdgpu_device *adev = ring->adev; in gmc_v11_0_emit_pasid_mapping() local
690 adev->vm_manager.vram_base_offset = adev->mmhub.funcs->get_mc_fb_offset(adev); in gmc_v11_0_vram_gtt_location()
721 adev->gmc.aper_base = adev->mmhub.funcs->get_mc_fb_offset(adev); in gmc_v11_0_mc_init()
767 adev->mmhub.funcs->init(adev); in gmc_v11_0_sw_init()
916 r = adev->mmhub.funcs->gart_enable(adev); in gmc_v11_0_gart_enable()
921 adev->hdp.funcs->flush_hdp(adev, NULL); in gmc_v11_0_gart_enable()
949 adev->umc.funcs->init_registers(adev); in gmc_v11_0_hw_init()
963 adev->mmhub.funcs->gart_disable(adev); in gmc_v11_0_gart_disable()
976 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); in gmc_v11_0_hw_fini()
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| H A D | soc21.c | 222 return adev->nbio.funcs->get_memsize(adev); in soc21_get_config_memsize()
437 adev->nbio.funcs->program_aspm(adev); in soc21_program_aspm()
574 adev->rev_id = amdgpu_device_get_rev_id(adev); in soc21_common_early_init()
620 adev->external_rev_id = adev->rev_id + 0x10; in soc21_common_early_init()
646 adev->external_rev_id = adev->rev_id + 0x1; in soc21_common_early_init()
661 adev->external_rev_id = adev->rev_id + 0x20; in soc21_common_early_init()
686 adev->external_rev_id = adev->rev_id + 0x80; in soc21_common_early_init()
762 adev->nbio.funcs->init_registers(adev); in soc21_common_hw_init()
768 adev->nbio.funcs->remap_hdp_registers(adev); in soc21_common_hw_init()
813 if (!(adev->flags & AMD_IS_APU) && adev->in_s3 && in soc21_need_reset_on_resume()
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| H A D | soc15.c | 320 return adev->nbio.funcs->get_memsize(adev); in soc15_get_config_memsize()
587 if (adev->flags & AMD_IS_APU && adev->in_s3 && in soc15_need_reset_on_resume()
674 adev->nbio.funcs->program_aspm(adev); in soc15_program_aspm()
1008 adev->external_rev_id = adev->rev_id + 0x14; in soc15_common_early_init()
1031 adev->external_rev_id = adev->rev_id + 0x28; in soc15_common_early_init()
1229 adev->df.funcs->sw_init(adev); in soc15_common_sw_init()
1240 adev->df.funcs->sw_fini(adev); in soc15_common_sw_fini()
1265 adev->nbio.funcs->init_registers(adev); in soc15_common_hw_init()
1408 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1426 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
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| H A D | amdgpu_rlc.c | 44 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
47 if (adev->cg_flags & in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_enter_safe_mode()
69 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
72 if (adev->cg_flags & in amdgpu_gfx_rlc_exit_safe_mode()
75 adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id); in amdgpu_gfx_rlc_exit_safe_mode()
105 amdgpu_gfx_rlc_fini(adev); in amdgpu_gfx_rlc_init_sr()
134 adev->gfx.rlc.clear_state_size = dws = adev->gfx.rlc.funcs->get_csb_size(adev); in amdgpu_gfx_rlc_init_csb()
162 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size, in amdgpu_gfx_rlc_init_cpt()
197 max_me = adev->gfx.rlc.funcs->get_cp_table_num(adev); in amdgpu_gfx_rlc_setup_cp_table()
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| H A D | nv.c | 309 return adev->nbio.funcs->get_memsize(adev); in nv_get_config_memsize()
521 adev->nbio.funcs->program_aspm(adev); in nv_program_aspm()
615 adev->nbio.funcs->enable_aspm(adev, !enter); in nv_update_umd_stable_pstate()
693 adev->external_rev_id = adev->rev_id + 0x1; in nv_common_early_init()
714 adev->external_rev_id = adev->rev_id + 20; in nv_common_early_init()
743 adev->external_rev_id = adev->rev_id + 0xa; in nv_common_early_init()
767 adev->external_rev_id = adev->rev_id + 0x28; in nv_common_early_init()
786 adev->external_rev_id = adev->rev_id + 0x32; in nv_common_early_init()
828 adev->external_rev_id = adev->rev_id + 0x3c; in nv_common_early_init()
1011 adev->nbio.funcs->init_registers(adev); in nv_common_hw_init()
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| H A D | amdgpu_discovery.c | 372 adev, adev->mman.discovery_bin); in amdgpu_discovery_init()
379 dev_err(adev->dev, in amdgpu_discovery_init()
662 adev->umc.active_mask = ((1 << adev->umc.node_inst_num) - 1) & in amdgpu_discovery_read_from_harvest_table()
910 struct amdgpu_device *adev = ip_top->adev; in ip_disc_release() local
1110 adev->ip_top = kzalloc(sizeof(*adev->ip_top), GFP_KERNEL); in amdgpu_discovery_sysfs_init()
1111 if (!adev->ip_top) in amdgpu_discovery_sysfs_init()
1114 adev->ip_top->adev = adev; in amdgpu_discovery_sysfs_init()
1275 adev->vcn.vcn_config[adev->vcn.num_vcn_inst] = in amdgpu_discovery_reg_base_init()
1553 adev->gmc.mall_size = mall_size_per_umc * adev->gmc.num_umc; in amdgpu_discovery_get_mall_info()
2029 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) in amdgpu_discovery_set_mm_ip_blocks()
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| H A D | amdgpu_acp.c | 105 adev->acp.parent = adev->dev; in acp_sw_init()
126 void *adev; member
136 adev = apd->adev; in acp_poweroff()
153 adev = apd->adev; in acp_poweron()
251 if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289) in acp_hw_init()
262 adev->acp.acp_genpd->adev = adev; in acp_hw_init()
308 adev->acp.acp_res[2].end = adev->acp.acp_res[2].start; in acp_hw_init()
312 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; in acp_hw_init()
313 adev->acp.acp_cell[0].platform_data = &adev->asic_type; in acp_hw_init()
416 adev->acp.acp_res[4].end = adev->acp.acp_res[4].start; in acp_hw_init()
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| H A D | amdgpu_virt.c | 66 adev->cg_flags = 0; in amdgpu_virt_init_setting()
67 adev->pg_flags = 0; in amdgpu_virt_init_setting()
232 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) in amdgpu_virt_alloc_mm_table()
260 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) in amdgpu_virt_free_mm_table()
526 adev->unique_id = in amdgpu_virt_read_pf2vf_data()
652 if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) { in amdgpu_virt_init_data_exchange()
654 } else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { in amdgpu_virt_init_data_exchange()
677 if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { in amdgpu_virt_exchange_data()
750 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) in amdgpu_detect_virtualization()
991 dev_err(adev->dev, in amdgpu_virt_rlcg_reg_rw()
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| H A D | amdgpu_ras.c | 141 if (adev && amdgpu_ras_get_context(adev)) in amdgpu_ras_set_error_query_ready()
147 if (adev && amdgpu_ras_get_context(adev)) in amdgpu_ras_get_error_query_ready()
663 obj->adev = adev; in amdgpu_ras_create_obj()
1068 adev->smuio.funcs->get_die_id(adev), in amdgpu_ras_query_error_status()
1088 adev->smuio.funcs->get_die_id(adev), in amdgpu_ras_query_error_status()
1340 struct amdgpu_device *adev = con->adev; in amdgpu_ras_sysfs_badpages_read() local
1669 struct amdgpu_device *adev = obj->adev; in amdgpu_ras_interrupt_poison_consumption_handler() local
2028 struct amdgpu_device *adev = ras->adev; in amdgpu_ras_do_recovery() local
2312 con->adev = adev; in amdgpu_ras_recovery_init()
2541 struct amdgpu_device *adev = con->adev; in amdgpu_ras_counte_dw() local
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| H A D | amdgpu_gfx.c | 214 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; in amdgpu_gfx_compute_queue_acquire()
315 ring->adev = NULL; in amdgpu_gfx_kiq_init_ring()
414 dev_warn(adev->dev, in amdgpu_gfx_mqd_sw_init()
559 if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang) in amdgpu_gfx_disable_kgq()
804 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); in amdgpu_gfx_ras_late_init()
826 if (!adev->gfx.ras) in amdgpu_gfx_ras_sw_init()
829 ras = adev->gfx.ras; in amdgpu_gfx_ras_sw_init()
856 if (adev->gfx.ras && adev->gfx.ras->poison_consumption_handler) in amdgpu_gfx_poison_consumption_handler()
857 return adev->gfx.ras->poison_consumption_handler(adev, entry); in amdgpu_gfx_poison_consumption_handler()
874 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops && in amdgpu_gfx_process_ras_data_cb()
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| H A D | amdgpu_bios.c | 105 adev->bios = NULL; in igp_read_bios_from_vram()
112 if (!adev->bios) { in igp_read_bios_from_vram()
133 adev->bios = NULL; in amdgpu_read_bios()
161 if (!adev->asic_funcs || !adev->asic_funcs->read_bios_from_rom) in amdgpu_read_bios_from_rom()
179 if (!adev->bios) { in amdgpu_read_bios_from_rom()
186 amdgpu_asic_read_bios_from_rom(adev, adev->bios, len); in amdgpu_read_bios_from_rom()
208 if (!adev->bios) in amdgpu_read_platform_bios()
468 adev->is_atom_fw = adev->asic_type >= CHIP_VEGA10; in amdgpu_get_bios()
498 adev->smuio.funcs->get_rom_index_offset(adev); in amdgpu_soc15_read_bios_from_rom()
500 adev->smuio.funcs->get_rom_data_offset(adev); in amdgpu_soc15_read_bios_from_rom()
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| H A D | amdgpu_amdkfd.c | 76 adev->kfd.dev = kgd2kfd_probe(adev, vf); in amdgpu_amdkfd_device_probe()
198 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, in amdgpu_amdkfd_device_init()
219 if (adev->kfd.dev) in amdgpu_amdkfd_interrupt()
225 if (adev->kfd.dev) in amdgpu_amdkfd_suspend()
233 if (adev->kfd.dev) in amdgpu_amdkfd_resume()
243 if (adev->kfd.dev) in amdgpu_amdkfd_pre_reset()
253 if (adev->kfd.dev) in amdgpu_amdkfd_post_reset()
427 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size) in amdgpu_amdkfd_get_local_mem_info()
457 return adev->gfx.funcs->get_gpu_clock_counter(adev); in amdgpu_amdkfd_get_gpu_clock_counter()
789 if (adev->gfx.ras && adev->gfx.ras->query_utcl2_poison_status) in amdgpu_amdkfd_ras_query_utcl2_poison_status()
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| H A D | vi.c | 1271 !(ASICID_IS_P23(adev->pdev->device, adev->pdev->revision))) || in vi_program_aspm()
1272 ASIC_IS_P22(adev->asic_type, adev->external_rev_id)) { in vi_program_aspm()
1481 adev->rev_id = vi_get_rev_id(adev); in vi_common_early_init()
1508 adev->external_rev_id = adev->rev_id + 0x3c; in vi_common_early_init()
1525 adev->external_rev_id = adev->rev_id + 0x14; in vi_common_early_init()
1548 adev->external_rev_id = adev->rev_id + 0x5A; in vi_common_early_init()
1571 adev->external_rev_id = adev->rev_id + 0x50; in vi_common_early_init()
1594 adev->external_rev_id = adev->rev_id + 0x64; in vi_common_early_init()
1618 adev->external_rev_id = adev->rev_id + 0x6E; in vi_common_early_init()
1645 adev->external_rev_id = adev->rev_id + 0x1; in vi_common_early_init()
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| H A D | mxgpu_nv.c | 148 r = xgpu_nv_poll_ack(adev); in xgpu_nv_mailbox_trans_msg()
348 if (amdgpu_sriov_runtime(adev) && !amdgpu_in_reset(adev)) in xgpu_nv_mailbox_rcv_irq()
350 &adev->virt.flr_work), in xgpu_nv_mailbox_rcv_irq()
390 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq); in xgpu_nv_mailbox_add_irq_id()
394 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); in xgpu_nv_mailbox_add_irq_id()
396 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_nv_mailbox_add_irq_id()
407 r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0); in xgpu_nv_mailbox_get_irq()
410 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_nv_mailbox_get_irq()
412 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_nv_mailbox_get_irq()
423 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_nv_mailbox_put_irq()
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| H A D | amdgpu_irq.c | 170 ret = amdgpu_ih_process(adev, &adev->irq.ih); in amdgpu_irq_handler()
191 amdgpu_ih_process(adev, &adev->irq.ih1); in amdgpu_irq_handle_ih1()
206 amdgpu_ih_process(adev, &adev->irq.ih2); in amdgpu_irq_handle_ih2()
221 amdgpu_ih_process(adev, &adev->irq.ih_soft); in amdgpu_irq_handle_ih_soft()
314 adev->irq.irq = irq; in amdgpu_irq_init()
325 free_irq(adev->irq.irq, adev_to_drm(adev)); in amdgpu_irq_fini_hw()
331 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); in amdgpu_irq_fini_hw()
332 amdgpu_ih_ring_fini(adev, &adev->irq.ih); in amdgpu_irq_fini_hw()
333 amdgpu_ih_ring_fini(adev, &adev->irq.ih1); in amdgpu_irq_fini_hw()
334 amdgpu_ih_ring_fini(adev, &adev->irq.ih2); in amdgpu_irq_fini_hw()
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| H A D | amdgpu_umc.c | 37 dev_warn(adev->dev, in amdgpu_umc_convert_error_address()
55 dev_warn(adev->dev, in amdgpu_umc_page_retirement_mca()
91 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_do_page_retirement()
95 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_do_page_retirement()
115 if (adev->umc.ras && in amdgpu_umc_do_page_retirement()
198 if (adev->virt.ops && adev->virt.ops->ras_poison_handler) in amdgpu_umc_poison_handler()
199 adev->virt.ops->ras_poison_handler(adev); in amdgpu_umc_poison_handler()
220 if (!adev->umc.ras) in amdgpu_umc_ras_sw_init()
223 ras = adev->umc.ras; in amdgpu_umc_ras_sw_init()
254 r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); in amdgpu_umc_ras_late_init()
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| H A D | vega20_reg_init.c | 29 int vega20_reg_base_init(struct amdgpu_device *adev) in vega20_reg_base_init() argument
58 void vega20_doorbell_index_init(struct amdgpu_device *adev) in vega20_doorbell_index_init() argument
60 adev->doorbell_index.kiq = AMDGPU_VEGA20_DOORBELL_KIQ; in vega20_doorbell_index_init()
61 adev->doorbell_index.mec_ring0 = AMDGPU_VEGA20_DOORBELL_MEC_RING0; in vega20_doorbell_index_init()
62 adev->doorbell_index.mec_ring1 = AMDGPU_VEGA20_DOORBELL_MEC_RING1; in vega20_doorbell_index_init()
63 adev->doorbell_index.mec_ring2 = AMDGPU_VEGA20_DOORBELL_MEC_RING2; in vega20_doorbell_index_init()
64 adev->doorbell_index.mec_ring3 = AMDGPU_VEGA20_DOORBELL_MEC_RING3; in vega20_doorbell_index_init()
65 adev->doorbell_index.mec_ring4 = AMDGPU_VEGA20_DOORBELL_MEC_RING4; in vega20_doorbell_index_init()
66 adev->doorbell_index.mec_ring5 = AMDGPU_VEGA20_DOORBELL_MEC_RING5; in vega20_doorbell_index_init()
80 adev->doorbell_index.ih = AMDGPU_VEGA20_DOORBELL_IH; in vega20_doorbell_index_init()
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| H A D | aqua_vanjaram.c | 66 return (adev->xcp_mgr->num_xcps > adev->vcn.num_vcn_inst); in aqua_vanjaram_xcp_vcn_shared()
309 struct amdgpu_device *adev = xcp_mgr->adev; in aqua_vanjaram_query_partition_mode() local
312 mode = adev->nbio.funcs->get_compute_partition_mode(adev); in aqua_vanjaram_query_partition_mode()
348 struct amdgpu_device *adev = xcp_mgr->adev; in __aqua_vanjaram_get_xcp_ip_info() local
411 struct amdgpu_device *adev = xcp_mgr->adev; in __aqua_vanjaram_get_auto_mode() local
435 struct amdgpu_device *adev = xcp_mgr->adev; in __aqua_vanjaram_is_valid_mode() local
498 adev = xcp_mgr->adev; in aqua_vanjaram_switch_partition_mode()
525 adev->gfx.funcs->switch_partition_mode(xcp_mgr->adev, in aqua_vanjaram_switch_partition_mode()
558 adev = xcp_mgr->adev; in aqua_vanjaram_get_xcp_mem_id()
637 adev->sdma.num_instances = NUM_SDMA(adev->sdma.sdma_mask); in aqua_vanjaram_init_soc_config()
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| H A D | sienna_cichlid.c | 40 adev->pm.fw_version >= 0x3a5500 && !amdgpu_sriov_vf(adev)) in sienna_cichlid_is_mode2_default()
85 r = adev->ip_blocks[i].version->funcs->suspend(adev); in sienna_cichlid_mode2_suspend_ip()
108 adev->gfxhub.funcs->mode2_save_regs(adev); in sienna_cichlid_mode2_prepare_hwcontext()
110 adev->gfxhub.funcs->halt(adev); in sienna_cichlid_mode2_prepare_hwcontext()
150 dev_err(adev->dev, in sienna_cichlid_mode2_perform_reset()
169 adev->gfxhub.funcs->mode2_restore_regs(adev); in sienna_cichlid_mode2_restore_ip()
170 adev->gfxhub.funcs->init(adev); in sienna_cichlid_mode2_restore_ip()
171 r = adev->gfxhub.funcs->gart_enable(adev); in sienna_cichlid_mode2_restore_ip()
179 r = adev->ip_blocks[i].version->funcs->resume(adev); in sienna_cichlid_mode2_restore_ip()
197 r = adev->ip_blocks[i].version->funcs->resume(adev); in sienna_cichlid_mode2_restore_ip()
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| H A D | amdgpu_doorbell_mgr.c | 38 if (amdgpu_device_skip_hw_access(adev)) in amdgpu_mm_rdoorbell()
60 if (amdgpu_device_skip_hw_access(adev)) in amdgpu_mm_wdoorbell()
80 if (amdgpu_device_skip_hw_access(adev)) in amdgpu_mm_rdoorbell64()
161 r = amdgpu_bo_create_kernel(adev, in amdgpu_doorbell_create_kernel_doorbells()
192 if (adev->asic_type < CHIP_BONAIRE) { in amdgpu_doorbell_init()
193 adev->doorbell.base = 0; in amdgpu_doorbell_init()
194 adev->doorbell.size = 0; in amdgpu_doorbell_init()
205 adev->doorbell.base = pci_resource_start(adev->pdev, 2); in amdgpu_doorbell_init()
206 adev->doorbell.size = pci_resource_len(adev->pdev, 2); in amdgpu_doorbell_init()
208 adev->doorbell.num_kernel_doorbells = in amdgpu_doorbell_init()
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| H A D | mxgpu_ai.c | 133 trn = xgpu_ai_peek_ack(adev); in xgpu_ai_mailbox_trans_msg()
156 r = xgpu_ai_poll_ack(adev); in xgpu_ai_mailbox_trans_msg()
320 if (amdgpu_sriov_runtime(adev) && !amdgpu_in_reset(adev)) in xgpu_ai_mailbox_rcv_irq()
365 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq); in xgpu_ai_mailbox_add_irq_id()
369 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); in xgpu_ai_mailbox_add_irq_id()
371 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_add_irq_id()
382 r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_get_irq()
385 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_get_irq()
387 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_get_irq()
398 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_put_irq()
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| /openbmc/linux/drivers/gpu/drm/amd/pm/ |
| H A D | amdgpu_dpm.c | 37 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
39 #define amdgpu_dpm_is_legacy_dpm(adev) ((adev)->powerplay.pp_handle == (adev)) argument
49 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_sclk()
65 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_mclk()
85 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_powergating_by_smu()
117 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_gfx_power_up_by_imu()
201 if (adev->in_s3) in amdgpu_dpm_is_baco_supported()
309 if (amdgpu_sriov_vf(adev)) in amdgpu_dpm_switch_power_profile()
431 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); in amdgpu_pm_acpi_event_handler()
1179 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; in amdgpu_dpm_set_sclk_od()
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