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/openbmc/qemu/target/openrisc/
H A Ddisas.c54 static bool trans_l_##opcode(disassemble_info *info, arg_l_##opcode *a) \
60 INSN(add, "r%d, r%d, r%d", a->d, a->a, a->b)
61 INSN(addc, "r%d, r%d, r%d", a->d, a->a, a->b)
62 INSN(sub, "r%d, r%d, r%d", a->d, a->a, a->b)
63 INSN(and, "r%d, r%d, r%d", a->d, a->a, a->b)
64 INSN(or, "r%d, r%d, r%d", a->d, a->a, a->b)
65 INSN(xor, "r%d, r%d, r%d", a->d, a->a, a->b)
66 INSN(sll, "r%d, r%d, r%d", a->d, a->a, a->b)
67 INSN(srl, "r%d, r%d, r%d", a->d, a->a, a->b)
68 INSN(sra, "r%d, r%d, r%d", a->d, a->a, a->b)
[all …]
H A Dtranslate.c419 static bool trans_l_add(DisasContext *dc, arg_dab *a) in trans_l_add() argument
421 check_r0_write(dc, a->d); in trans_l_add()
422 gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_add()
426 static bool trans_l_addc(DisasContext *dc, arg_dab *a) in trans_l_addc() argument
428 check_r0_write(dc, a->d); in trans_l_addc()
429 gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_addc()
433 static bool trans_l_sub(DisasContext *dc, arg_dab *a) in trans_l_sub() argument
435 check_r0_write(dc, a->d); in trans_l_sub()
436 gen_sub(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b)); in trans_l_sub()
440 static bool trans_l_and(DisasContext *dc, arg_dab *a) in trans_l_and() argument
[all …]
H A Dinsns.decode16 # You should have received a copy of the GNU Lesser General Public
20 &dab d a b
21 &da d a
22 &ab a b
23 &dal d a l
24 &ai a i
25 &dab_pair d a b dp ap bp
26 &ab_pair a b ap bp
27 &da_pair d a dp ap
57 &load d a i
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/openbmc/qemu/target/rx/
H A Ddisas.c196 static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a) in trans_MOV_rm() argument
198 if (a->dsp > 0) { in trans_MOV_rm()
200 size[a->sz], a->rs, a->dsp << a->sz, a->rd); in trans_MOV_rm()
203 size[a->sz], a->rs, a->rd); in trans_MOV_rm()
209 static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a) in trans_MOV_mr() argument
211 if (a->dsp > 0) { in trans_MOV_mr()
213 size[a->sz], a->dsp << a->sz, a->rs, a->rd); in trans_MOV_mr()
216 size[a->sz], a->rs, a->rd); in trans_MOV_mr()
224 static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a) in trans_MOV_ir() argument
226 prt_ir(ctx, "mov.l", a->imm, a->rd); in trans_MOV_ir()
[all …]
H A Dtranslate.c430 static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a) in trans_MOV_rm() argument
434 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); in trans_MOV_rm()
435 rx_gen_st(a->sz, cpu_regs[a->rs], mem); in trans_MOV_rm()
440 static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a) in trans_MOV_mr() argument
444 tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); in trans_MOV_mr()
445 rx_gen_ld(a->sz, cpu_regs[a->rd], mem); in trans_MOV_mr()
452 static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a) in trans_MOV_ir() argument
454 tcg_gen_movi_i32(cpu_regs[a->rd], a->imm); in trans_MOV_ir()
460 static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a) in trans_MOV_im() argument
463 imm = tcg_constant_i32(a->imm); in trans_MOV_im()
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/openbmc/qemu/include/qemu/
H A Dint128.h15 static inline Int128 int128_make64(uint64_t a) in int128_make64() argument
17 return a; in int128_make64()
20 static inline Int128 int128_makes64(int64_t a) in int128_makes64() argument
22 return a; in int128_makes64()
30 static inline uint64_t int128_get64(Int128 a) in int128_get64() argument
32 uint64_t r = a; in int128_get64()
33 assert(r == a); in int128_get64()
37 static inline uint64_t int128_getlo(Int128 a) in int128_getlo() argument
39 return a; in int128_getlo()
42 static inline int64_t int128_gethi(Int128 a) in int128_gethi() argument
[all …]
/openbmc/qemu/target/avr/
H A Ddisas.c104 static bool trans_##opcode(DisasContext *pctx, arg_##opcode * a) \
111 static bool trans_##opcode(DisasContext *pctx, arg_##opcode * a) \
140 INSN(ADD, "r%d, r%d", a->rd, a->rr)
141 INSN(ADC, "r%d, r%d", a->rd, a->rr)
142 INSN(ADIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm)
143 INSN(SUB, "r%d, r%d", a->rd, a->rr)
144 INSN(SUBI, "r%d, %d", a->rd, a->imm)
145 INSN(SBC, "r%d, r%d", a->rd, a->rr)
146 INSN(SBCI, "r%d, %d", a->rd, a->imm)
147 INSN(SBIW, "r%d:r%d, %d", a->rd + 1, a->rd, a->imm)
[all …]
/openbmc/qemu/target/hexagon/
H A Dfma_emu.c93 static Int128 int128_sub_borrow(Int128 a, Int128 b, int borrow) in int128_sub_borrow() argument
95 Int128 ret = int128_sub(a, b); in int128_sub_borrow()
121 static Accum accum_norm_left(Accum a) in accum_norm_left() argument
123 a.exp--; in accum_norm_left()
124 a.mant = int128_lshift(a.mant, 1); in accum_norm_left()
125 a.mant = int128_or(a.mant, int128_make64(a.guard)); in accum_norm_left()
126 a.guard = a.round; in accum_norm_left()
127 a.round = a.sticky; in accum_norm_left()
128 return a; in accum_norm_left()
132 static inline Accum accum_norm_right(Accum a, int amt) in accum_norm_right() argument
[all …]
/openbmc/qemu/target/mips/tcg/
H A Dtx79_translate.c65 static bool trans_MFHI1(DisasContext *ctx, arg_r *a) in trans_MFHI1() argument
67 gen_store_gpr(cpu_HI[1], a->rd); in trans_MFHI1()
72 static bool trans_MFLO1(DisasContext *ctx, arg_r *a) in trans_MFLO1() argument
74 gen_store_gpr(cpu_LO[1], a->rd); in trans_MFLO1()
79 static bool trans_MTHI1(DisasContext *ctx, arg_r *a) in trans_MTHI1() argument
81 gen_load_gpr(cpu_HI[1], a->rs); in trans_MTHI1()
86 static bool trans_MTLO1(DisasContext *ctx, arg_r *a) in trans_MTLO1() argument
88 gen_load_gpr(cpu_LO[1], a->rs); in trans_MTLO1()
117 static bool trans_parallel_arith(DisasContext *ctx, arg_r *a, in trans_parallel_arith() argument
122 if (a->rd == 0) { in trans_parallel_arith()
[all …]
H A Docteon_translate.c16 static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) in trans_BBIT() argument
29 gen_load_gpr(t0, a->rs); in trans_BBIT()
31 p = tcg_constant_tl(1ULL << a->p); in trans_BBIT()
32 if (a->set) { in trans_BBIT()
39 ctx->btarget = ctx->base.pc_next + 4 + a->offset * 4; in trans_BBIT()
44 static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a) in trans_BADDU() argument
48 if (a->rt == 0) { in trans_BADDU()
55 gen_load_gpr(t0, a->rs); in trans_BADDU()
56 gen_load_gpr(t1, a->rt); in trans_BADDU()
59 tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff); in trans_BADDU()
[all …]
/openbmc/openbmc/poky/bitbake/lib/toaster/toastergui/static/js/
H A Dui-bootstrap-tpls-0.11.0.js8 …a,b,c){function d(a){for(var b in a)if(void 0!==f.style[b])return a[b]}var e=function(d,f,g){g=g||… argument
9 …a.replace(b,function(a,b){return(b?c:"")+a.toLowerCase()})}var b={placement:"top",animation:!0,pop… argument
H A Dui-bootstrap-tpls-0.11.0.min.js8 …a,b,c){function d(a){for(var b in a)if(void 0!==f.style[b])return a[b]}var e=function(d,f,g){g=g||… argument
9 …a.replace(b,function(a,b){return(b?c:"")+a.toLowerCase()})}var b={placement:"top",animation:!0,pop… argument
/openbmc/qemu/target/arm/tcg/
H A Darith_helper.c24 static inline uint16_t add16_sat(uint16_t a, uint16_t b) in add16_sat() argument
28 res = a + b; in add16_sat()
29 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) { in add16_sat()
30 if (a & 0x8000) { in add16_sat()
40 static inline uint8_t add8_sat(uint8_t a, uint8_t b) in add8_sat() argument
44 res = a + b; in add8_sat()
45 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) { in add8_sat()
46 if (a & 0x80) { in add8_sat()
56 static inline uint16_t sub16_sat(uint16_t a, uint16_t b) in sub16_sat() argument
60 res = a - b; in sub16_sat()
[all …]
H A Dtranslate-neon.c215 static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) in trans_VCMLA() argument
220 if (a->size == MO_16) { in trans_VCMLA()
224 return do_neon_ddda_fpst(s, a->q * 7, a->vd, a->vn, a->vm, a->rot, in trans_VCMLA()
227 return do_neon_ddda_fpst(s, a->q * 7, a->vd, a->vn, a->vm, a->rot, in trans_VCMLA()
231 static bool trans_VCADD(DisasContext *s, arg_VCADD *a) in trans_VCADD() argument
238 || (a->size == MO_16 && !dc_isar_feature(aa32_fp16_arith, s))) { in trans_VCADD()
244 ((a->vd | a->vn | a->vm) & 0x10)) { in trans_VCADD()
248 if ((a->vn | a->vm | a->vd) & a->q) { in trans_VCADD()
256 opr_sz = (1 + a->q) * 8; in trans_VCADD()
257 fpst = fpstatus_ptr(a->size == MO_16 ? FPST_STD_F16 : FPST_STD); in trans_VCADD()
[all …]
H A Dtranslate-sme.c151 static bool trans_ZERO(DisasContext *s, arg_ZERO *a) in trans_ZERO() argument
157 gen_helper_sme_zero(tcg_env, tcg_constant_i32(a->imm), in trans_ZERO()
163 static bool trans_ZERO_zt0(DisasContext *s, arg_ZERO_zt0 *a) in trans_ZERO_zt0() argument
176 static bool trans_ZERO_za(DisasContext *s, arg_ZERO_za *a) in trans_ZERO_za() argument
183 int vstride = svl / a->ngrp; in trans_ZERO_za()
184 TCGv_ptr t_za = get_zarray(s, a->rv, a->off, a->ngrp, a->nvec); in trans_ZERO_za()
186 for (int r = 0; r < a->ngrp; ++r) { in trans_ZERO_za()
187 for (int i = 0; i < a->nvec; ++i) { in trans_ZERO_za()
196 static bool do_mova_tile(DisasContext *s, arg_mova_p *a, bool to_vec) in do_mova_tile() argument
222 t_za = get_tile_rowcol(s, a->esz, a->rs, a->za, a->off, 1, 0, a->v); in do_mova_tile()
[all …]
H A Dtranslate-a64.c1535 static bool do_gvec_op2_ool(DisasContext *s, arg_qrr_e *a, int data, in do_gvec_op2_ool() argument
1538 if (!a->q && a->esz == MO_64) { in do_gvec_op2_ool()
1542 gen_gvec_op2_ool(s, a->q, a->rd, a->rn, data, fn); in do_gvec_op2_ool()
1547 static bool do_gvec_op3_ool(DisasContext *s, arg_qrrr_e *a, int data, in do_gvec_op3_ool() argument
1550 if (!a->q && a->esz == MO_64) { in do_gvec_op3_ool()
1554 gen_gvec_op3_ool(s, a->q, a->rd, a->rn, a->rm, data, fn); in do_gvec_op3_ool()
1559 static bool do_gvec_fn3(DisasContext *s, arg_qrrr_e *a, GVecGen3Fn *fn) in do_gvec_fn3() argument
1561 if (!a->q && a->esz == MO_64) { in do_gvec_fn3()
1565 gen_gvec_fn3(s, a->q, a->rd, a->rn, a->rm, fn, a->esz); in do_gvec_fn3()
1570 static bool do_gvec_fn3_no64(DisasContext *s, arg_qrrr_e *a, GVecGen3Fn *fn) in do_gvec_fn3_no64() argument
[all …]
H A Dtranslate-mve.c144 static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn, in do_ldst() argument
152 !mve_check_qreg_bank(s, a->qd) || in do_ldst()
158 if (a->rn == 15 || (a->rn == 13 && a->w)) { in do_ldst()
166 offset = a->imm << msize; in do_ldst()
167 if (!a->a) { in do_ldst()
170 addr = load_reg(s, a->rn); in do_ldst()
171 if (a->p) { in do_ldst()
175 qreg = mve_qreg_ptr(a->qd); in do_ldst()
182 if (a->w) { in do_ldst()
183 if (!a->p) { in do_ldst()
[all …]
/openbmc/u-boot/lib/zlib/
H A Dadler32.c23 # define MOD(a) \ argument
25 if (a >= (BASE << 16)) a -= (BASE << 16); \
26 if (a >= (BASE << 15)) a -= (BASE << 15); \
27 if (a >= (BASE << 14)) a -= (BASE << 14); \
28 if (a >= (BASE << 13)) a -= (BASE << 13); \
29 if (a >= (BASE << 12)) a -= (BASE << 12); \
30 if (a >= (BASE << 11)) a -= (BASE << 11); \
31 if (a >= (BASE << 10)) a -= (BASE << 10); \
32 if (a >= (BASE << 9)) a -= (BASE << 9); \
33 if (a >= (BASE << 8)) a -= (BASE << 8); \
[all …]
/openbmc/rest-dbus/resources/
H A Djquery.min.js2 …a,b){"object"==typeof module&&"object"==typeof module.exports?module.exports=a.document?b(a,!0):fu… argument
4 …a,b,d,e){if(m.acceptData(a)){var f,g,h=m.expando,i=a.nodeType,j=i?m.cache:a,k=i?a[h]:a[h]&&h;if(k&… argument
5 …a,b,c,d,e)}m.Tween=Za,Za.prototype={constructor:Za,init:function(a,b,c,d,e,f){this.elem=a,this.pro… argument
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvd.c.inc17 * You should have received a copy of the GNU General Public License along with
42 static bool trans_fld(DisasContext *ctx, arg_fld *a)
65 addr = get_address(ctx, a->rs1, a->imm);
66 tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, memop);
72 static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
89 addr = get_address(ctx, a->rs1, a->imm);
90 tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, memop);
94 static bool trans_c_fld(DisasContext *ctx, arg_fld *a)
97 return trans_fld(ctx, a);
100 static bool trans_c_fsd(DisasContext *ctx, arg_fsd *a)
[all …]
/openbmc/qemu/target/loongarch/
H A Dvec.h33 #define DO_ADD(a, b) (a + b) argument
34 #define DO_SUB(a, b) (a - b) argument
35 #define DO_VAVG(a, b) ((a >> 1) + (b >> 1) + (a & b & 1)) argument
36 #define DO_VAVGR(a, b) ((a >> 1) + (b >> 1) + ((a | b) & 1)) argument
37 #define DO_VABSD(a, b) ((a > b) ? (a -b) : (b-a)) argument
38 #define DO_VABS(a) ((a < 0) ? (-a) : (a)) argument
39 #define DO_MIN(a, b) (a < b ? a : b) argument
40 #define DO_MAX(a, b) (a > b ? a : b) argument
41 #define DO_MUL(a, b) (a * b) argument
42 #define DO_MADD(a, b, c) (a + b * c) argument
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/arm/
H A Darch-armv8-3a.inc1 DEFAULTTUNE ?= "armv8-3a"
3 TUNEVALID[armv8-3a] = "Enable instructions for ARMv8.3-a"
4 TUNE_CCARGS_MARCH .= "${@bb.utils.contains('TUNE_FEATURES', 'armv8-3a', ' -march=armv8.3-a', '', d)…
6 MACHINEOVERRIDES =. "${@bb.utils.contains('TUNE_FEATURES', 'armv8-3a', 'armv8-3a:', '', d)}"
10 AVAILTUNES += "armv8-3a armv8-3a-crypto armv8-3a-crypto-sve"
11 ARMPKGARCH:tune-armv8-3a ?= "armv8-3a"
12 ARMPKGARCH:tune-armv8-3a-crypto ?= "armv8-3a"
13 ARMPKGARCH:tune-armv8-3a-crypto-sve ?= "armv8-3a"
14 TUNE_FEATURES:tune-armv8-3a = "aarch64 armv8-3a"
15 TUNE_FEATURES:tune-armv8-3a-crypto = "${TUNE_FEATURES:tune-armv8-3a} crypto"
[all …]
H A Darch-armv8-6a.inc1 DEFAULTTUNE ?= "armv8-6a"
3 TUNEVALID[armv8-6a] = "Enable instructions for ARMv8.6-a"
4 TUNE_CCARGS_MARCH .= "${@bb.utils.contains('TUNE_FEATURES', 'armv8-6a', ' -march=armv8.6-a', '', d)…
6 MACHINEOVERRIDES =. "${@bb.utils.contains('TUNE_FEATURES', 'armv8-6a', 'armv8-6a:', '', d)}"
10 AVAILTUNES += "armv8-6a armv8-6a-crypto armv8-6a-crypto-sve"
11 ARMPKGARCH:tune-armv8-6a ?= "armv8-6a"
12 ARMPKGARCH:tune-armv8-6a-crypto ?= "armv8-6a"
13 ARMPKGARCH:tune-armv8-6a-crypto-sve ?= "armv8-6a"
14 TUNE_FEATURES:tune-armv8-6a = "aarch64 armv8-6a"
15 TUNE_FEATURES:tune-armv8-6a-crypto = "${TUNE_FEATURES:tune-armv8-6a} crypto"
[all …]
/openbmc/u-boot/arch/mips/include/asm/
H A Daddrspace.h45 #define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) argument
50 #define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) argument
51 #define XPHYSADDR(a) ((_ACAST64_(a)) & \ argument
70 #define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) argument
71 #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) argument
72 #define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) argument
73 #define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) argument
77 #define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) argument
78 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) argument
79 #define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2) argument
[all …]
/openbmc/u-boot/drivers/net/
H A Dsmc91111.h71 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1)))) argument
72 #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) argument
73 #define SMC_inb(a,p) ({ \ argument
74 unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \
80 #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) argument
81 #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) argument
82 #define SMC_inb(a,p) ({ \ argument
83 unsigned int __p = (unsigned int)((a)->iobase + (p)); \
91 #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) argument
92 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d) argument
[all …]

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