1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 22439e4bfSJean-Christophe PLAGNIOL-VILLARD /*------------------------------------------------------------------------ 32439e4bfSJean-Christophe PLAGNIOL-VILLARD . smc91111.h - macros for the LAN91C111 Ethernet Driver 42439e4bfSJean-Christophe PLAGNIOL-VILLARD . 52439e4bfSJean-Christophe PLAGNIOL-VILLARD . (C) Copyright 2002 62439e4bfSJean-Christophe PLAGNIOL-VILLARD . Sysgo Real-Time Solutions, GmbH <www.elinos.com> 72439e4bfSJean-Christophe PLAGNIOL-VILLARD . Rolf Offermanns <rof@sysgo.de> 82439e4bfSJean-Christophe PLAGNIOL-VILLARD . Copyright (C) 2001 Standard Microsystems Corporation (SMSC) 92439e4bfSJean-Christophe PLAGNIOL-VILLARD . Developed by Simple Network Magic Corporation (SNMC) 102439e4bfSJean-Christophe PLAGNIOL-VILLARD . Copyright (C) 1996 by Erik Stahlman (ES) 112439e4bfSJean-Christophe PLAGNIOL-VILLARD . 122439e4bfSJean-Christophe PLAGNIOL-VILLARD . This file contains register information and access macros for 132439e4bfSJean-Christophe PLAGNIOL-VILLARD . the LAN91C111 single chip ethernet controller. It is a modified 142439e4bfSJean-Christophe PLAGNIOL-VILLARD . version of the smc9194.h file. 152439e4bfSJean-Christophe PLAGNIOL-VILLARD . 162439e4bfSJean-Christophe PLAGNIOL-VILLARD . Information contained in this file was obtained from the LAN91C111 172439e4bfSJean-Christophe PLAGNIOL-VILLARD . manual from SMC. To get a copy, if you really want one, you can find 182439e4bfSJean-Christophe PLAGNIOL-VILLARD . information under www.smsc.com. 192439e4bfSJean-Christophe PLAGNIOL-VILLARD . 202439e4bfSJean-Christophe PLAGNIOL-VILLARD . Authors 212439e4bfSJean-Christophe PLAGNIOL-VILLARD . Erik Stahlman ( erik@vt.edu ) 222439e4bfSJean-Christophe PLAGNIOL-VILLARD . Daris A Nevil ( dnevil@snmc.com ) 232439e4bfSJean-Christophe PLAGNIOL-VILLARD . 242439e4bfSJean-Christophe PLAGNIOL-VILLARD . History 252439e4bfSJean-Christophe PLAGNIOL-VILLARD . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device 262439e4bfSJean-Christophe PLAGNIOL-VILLARD . 272439e4bfSJean-Christophe PLAGNIOL-VILLARD ---------------------------------------------------------------------------*/ 282439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifndef _SMC91111_H_ 292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define _SMC91111_H_ 302439e4bfSJean-Christophe PLAGNIOL-VILLARD 312439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <asm/types.h> 322439e4bfSJean-Christophe PLAGNIOL-VILLARD #include <config.h> 332439e4bfSJean-Christophe PLAGNIOL-VILLARD 342439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 352439e4bfSJean-Christophe PLAGNIOL-VILLARD * This function may be called by the board specific initialisation code 362439e4bfSJean-Christophe PLAGNIOL-VILLARD * in order to override the default mac address. 372439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 382439e4bfSJean-Christophe PLAGNIOL-VILLARD 392439e4bfSJean-Christophe PLAGNIOL-VILLARD void smc_set_mac_addr (const unsigned char *addr); 402439e4bfSJean-Christophe PLAGNIOL-VILLARD 412439e4bfSJean-Christophe PLAGNIOL-VILLARD 422439e4bfSJean-Christophe PLAGNIOL-VILLARD /* I want some simple types */ 432439e4bfSJean-Christophe PLAGNIOL-VILLARD 442439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef unsigned char byte; 452439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef unsigned short word; 462439e4bfSJean-Christophe PLAGNIOL-VILLARD typedef unsigned long int dword; 472439e4bfSJean-Christophe PLAGNIOL-VILLARD 487194ab80SBen Warren struct smc91111_priv{ 497194ab80SBen Warren u8 dev_num; 507194ab80SBen Warren }; 517194ab80SBen Warren 522439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 532439e4bfSJean-Christophe PLAGNIOL-VILLARD . DEBUGGING LEVELS 542439e4bfSJean-Christophe PLAGNIOL-VILLARD . 552439e4bfSJean-Christophe PLAGNIOL-VILLARD . 0 for normal operation 562439e4bfSJean-Christophe PLAGNIOL-VILLARD . 1 for slightly more details 572439e4bfSJean-Christophe PLAGNIOL-VILLARD . >2 for various levels of increasingly useless information 582439e4bfSJean-Christophe PLAGNIOL-VILLARD . 2 for interrupt tracking, status flags 592439e4bfSJean-Christophe PLAGNIOL-VILLARD . 3 for packet info 602439e4bfSJean-Christophe PLAGNIOL-VILLARD . 4 for complete packet dumps 612439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 622439e4bfSJean-Christophe PLAGNIOL-VILLARD /*#define SMC_DEBUG 0 */ 632439e4bfSJean-Christophe PLAGNIOL-VILLARD 642439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */ 652439e4bfSJean-Christophe PLAGNIOL-VILLARD 662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_IO_EXTENT 16 672439e4bfSJean-Christophe PLAGNIOL-VILLARD 68abc20abaSMarek Vasut #ifdef CONFIG_CPU_PXA25X 692439e4bfSJean-Christophe PLAGNIOL-VILLARD 702439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_XSENGINE 711031ae96SBen Warren #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+((r)<<1)))) 721031ae96SBen Warren #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) 737194ab80SBen Warren #define SMC_inb(a,p) ({ \ 741031ae96SBen Warren unsigned int __p = (unsigned int)((a)->iobase + ((p)<<1)); \ 752439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \ 762439e4bfSJean-Christophe PLAGNIOL-VILLARD if (__p & 2) __v >>= 8; \ 772439e4bfSJean-Christophe PLAGNIOL-VILLARD else __v &= 0xff; \ 782439e4bfSJean-Christophe PLAGNIOL-VILLARD __v; }) 792439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 807194ab80SBen Warren #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) 817194ab80SBen Warren #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) 827194ab80SBen Warren #define SMC_inb(a,p) ({ \ 837194ab80SBen Warren unsigned int __p = (unsigned int)((a)->iobase + (p)); \ 842439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \ 852439e4bfSJean-Christophe PLAGNIOL-VILLARD if (__p & 1) __v >>= 8; \ 862439e4bfSJean-Christophe PLAGNIOL-VILLARD else __v &= 0xff; \ 872439e4bfSJean-Christophe PLAGNIOL-VILLARD __v; }) 882439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 892439e4bfSJean-Christophe PLAGNIOL-VILLARD 902439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_XSENGINE 917194ab80SBen Warren #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) 927194ab80SBen Warren #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d) 932439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 947194ab80SBen Warren #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) 957194ab80SBen Warren #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) 962439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 972439e4bfSJean-Christophe PLAGNIOL-VILLARD 987194ab80SBen Warren #define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ 997194ab80SBen Warren word __w = SMC_inw((a),(r)&~1); \ 1002439e4bfSJean-Christophe PLAGNIOL-VILLARD __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 1012439e4bfSJean-Christophe PLAGNIOL-VILLARD __w |= ((r)&1) ? __d<<8 : __d; \ 1027194ab80SBen Warren SMC_outw((a),__w,(r)&~1); \ 1032439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 1042439e4bfSJean-Christophe PLAGNIOL-VILLARD 1057194ab80SBen Warren #define SMC_outsl(a,r,b,l) ({ int __i; \ 1062439e4bfSJean-Christophe PLAGNIOL-VILLARD dword *__b2; \ 1072439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (dword *) b; \ 1082439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 1097194ab80SBen Warren SMC_outl((a), *(__b2 + __i), r); \ 1102439e4bfSJean-Christophe PLAGNIOL-VILLARD } \ 1112439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 1122439e4bfSJean-Christophe PLAGNIOL-VILLARD 1137194ab80SBen Warren #define SMC_outsw(a,r,b,l) ({ int __i; \ 1142439e4bfSJean-Christophe PLAGNIOL-VILLARD word *__b2; \ 1152439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (word *) b; \ 1162439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 1177194ab80SBen Warren SMC_outw((a), *(__b2 + __i), r); \ 1182439e4bfSJean-Christophe PLAGNIOL-VILLARD } \ 1192439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 1202439e4bfSJean-Christophe PLAGNIOL-VILLARD 1217194ab80SBen Warren #define SMC_insl(a,r,b,l) ({ int __i ; \ 1222439e4bfSJean-Christophe PLAGNIOL-VILLARD dword *__b2; \ 1232439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (dword *) b; \ 1242439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 1257194ab80SBen Warren *(__b2 + __i) = SMC_inl((a),(r)); \ 1267194ab80SBen Warren SMC_inl((a),0); \ 1272439e4bfSJean-Christophe PLAGNIOL-VILLARD }; \ 1282439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 1292439e4bfSJean-Christophe PLAGNIOL-VILLARD 1307194ab80SBen Warren #define SMC_insw(a,r,b,l) ({ int __i ; \ 1312439e4bfSJean-Christophe PLAGNIOL-VILLARD word *__b2; \ 1322439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (word *) b; \ 1332439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 1347194ab80SBen Warren *(__b2 + __i) = SMC_inw((a),(r)); \ 1357194ab80SBen Warren SMC_inw((a),0); \ 1362439e4bfSJean-Christophe PLAGNIOL-VILLARD }; \ 1372439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 1382439e4bfSJean-Christophe PLAGNIOL-VILLARD 1397194ab80SBen Warren #define SMC_insb(a,r,b,l) ({ int __i ; \ 1402439e4bfSJean-Christophe PLAGNIOL-VILLARD byte *__b2; \ 1412439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (byte *) b; \ 1422439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 1437194ab80SBen Warren *(__b2 + __i) = SMC_inb((a),(r)); \ 1447194ab80SBen Warren SMC_inb((a),0); \ 1452439e4bfSJean-Christophe PLAGNIOL-VILLARD }; \ 1462439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 1472439e4bfSJean-Christophe PLAGNIOL-VILLARD 148abc20abaSMarek Vasut #elif defined(CONFIG_LEON) /* if not CONFIG_CPU_PXA25X */ 1493eac6402SDaniel Hellstrom 1503eac6402SDaniel Hellstrom #define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); }) 1513eac6402SDaniel Hellstrom 1523eac6402SDaniel Hellstrom #define SMC_LEON_SWAP32(_x_) \ 1533eac6402SDaniel Hellstrom ({ dword _x = (_x_); \ 1543eac6402SDaniel Hellstrom ((_x << 24) | \ 1553eac6402SDaniel Hellstrom ((0x0000FF00UL & _x) << 8) | \ 1563eac6402SDaniel Hellstrom ((0x00FF0000UL & _x) >> 8) | \ 1573eac6402SDaniel Hellstrom (_x >> 24)); }) 1583eac6402SDaniel Hellstrom 1597194ab80SBen Warren #define SMC_inl(a,r) (SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0))))) 1607194ab80SBen Warren #define SMC_inl_nosw(a,r) ((*(volatile dword *)((a)->iobase+((r)<<0)))) 1617194ab80SBen Warren #define SMC_inw(a,r) (SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0))))) 1627194ab80SBen Warren #define SMC_inw_nosw(a,r) ((*(volatile word *)((a)->iobase+((r)<<0)))) 1637194ab80SBen Warren #define SMC_inb(a,p) ({ \ 1647194ab80SBen Warren word ___v = SMC_inw((a),(p) & ~1); \ 1653eac6402SDaniel Hellstrom if ((p) & 1) ___v >>= 8; \ 1663eac6402SDaniel Hellstrom else ___v &= 0xff; \ 1673eac6402SDaniel Hellstrom ___v; }) 1683eac6402SDaniel Hellstrom 1697194ab80SBen Warren #define SMC_outl(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d)) 1707194ab80SBen Warren #define SMC_outl_nosw(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=(d)) 1717194ab80SBen Warren #define SMC_outw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d)) 1727194ab80SBen Warren #define SMC_outw_nosw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=(d)) 1737194ab80SBen Warren #define SMC_outb(a,d,r) do{ word __d = (byte)(d); \ 1747194ab80SBen Warren word __w = SMC_inw((a),(r)&~1); \ 1753eac6402SDaniel Hellstrom __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 1763eac6402SDaniel Hellstrom __w |= ((r)&1) ? __d<<8 : __d; \ 1777194ab80SBen Warren SMC_outw((a),__w,(r)&~1); \ 1783eac6402SDaniel Hellstrom }while(0) 1797194ab80SBen Warren #define SMC_outsl(a,r,b,l) do{ int __i; \ 1803eac6402SDaniel Hellstrom dword *__b2; \ 1813eac6402SDaniel Hellstrom __b2 = (dword *) b; \ 1823eac6402SDaniel Hellstrom for (__i = 0; __i < l; __i++) { \ 1837194ab80SBen Warren SMC_outl_nosw((a), *(__b2 + __i), r); \ 1843eac6402SDaniel Hellstrom } \ 1853eac6402SDaniel Hellstrom }while(0) 1867194ab80SBen Warren #define SMC_outsw(a,r,b,l) do{ int __i; \ 1873eac6402SDaniel Hellstrom word *__b2; \ 1883eac6402SDaniel Hellstrom __b2 = (word *) b; \ 1893eac6402SDaniel Hellstrom for (__i = 0; __i < l; __i++) { \ 1907194ab80SBen Warren SMC_outw_nosw((a), *(__b2 + __i), r); \ 1913eac6402SDaniel Hellstrom } \ 1923eac6402SDaniel Hellstrom }while(0) 1937194ab80SBen Warren #define SMC_insl(a,r,b,l) do{ int __i ; \ 1943eac6402SDaniel Hellstrom dword *__b2; \ 1953eac6402SDaniel Hellstrom __b2 = (dword *) b; \ 1963eac6402SDaniel Hellstrom for (__i = 0; __i < l; __i++) { \ 1977194ab80SBen Warren *(__b2 + __i) = SMC_inl_nosw((a),(r)); \ 1983eac6402SDaniel Hellstrom }; \ 1993eac6402SDaniel Hellstrom }while(0) 2003eac6402SDaniel Hellstrom 2017194ab80SBen Warren #define SMC_insw(a,r,b,l) do{ int __i ; \ 2023eac6402SDaniel Hellstrom word *__b2; \ 2033eac6402SDaniel Hellstrom __b2 = (word *) b; \ 2043eac6402SDaniel Hellstrom for (__i = 0; __i < l; __i++) { \ 2057194ab80SBen Warren *(__b2 + __i) = SMC_inw_nosw((a),(r)); \ 2063eac6402SDaniel Hellstrom }; \ 2073eac6402SDaniel Hellstrom }while(0) 2083eac6402SDaniel Hellstrom 2097194ab80SBen Warren #define SMC_insb(a,r,b,l) do{ int __i ; \ 2103eac6402SDaniel Hellstrom byte *__b2; \ 2113eac6402SDaniel Hellstrom __b2 = (byte *) b; \ 2123eac6402SDaniel Hellstrom for (__i = 0; __i < l; __i++) { \ 2137194ab80SBen Warren *(__b2 + __i) = SMC_inb((a),(r)); \ 2143eac6402SDaniel Hellstrom }; \ 2153eac6402SDaniel Hellstrom }while(0) 216e9efe16dSYoshinori Sato #elif defined(CONFIG_MS7206SE) 217e9efe16dSYoshinori Sato #define SWAB7206(x) ({ word __x = x; ((__x << 8)|(__x >> 8)); }) 218e9efe16dSYoshinori Sato #define SMC_inw(a, r) *((volatile word*)((a)->iobase + (r))) 219e9efe16dSYoshinori Sato #define SMC_inb(a, r) (*((volatile byte*)((a)->iobase + ((r) ^ 0x01)))) 220e9efe16dSYoshinori Sato #define SMC_insw(a, r, b, l) \ 221e9efe16dSYoshinori Sato do { \ 222e9efe16dSYoshinori Sato int __i; \ 223e9efe16dSYoshinori Sato word *__b2 = (word *)(b); \ 224e9efe16dSYoshinori Sato for (__i = 0; __i < (l); __i++) { \ 225e9efe16dSYoshinori Sato *__b2++ = SWAB7206(SMC_inw(a, r)); \ 226e9efe16dSYoshinori Sato } \ 227e9efe16dSYoshinori Sato } while (0) 228e9efe16dSYoshinori Sato #define SMC_outw(a, d, r) (*((volatile word *)((a)->iobase+(r))) = d) 229e9efe16dSYoshinori Sato #define SMC_outb(a, d, r) ({ word __d = (byte)(d); \ 230e9efe16dSYoshinori Sato word __w = SMC_inw((a), ((r)&(~1))); \ 231e9efe16dSYoshinori Sato if (((r) & 1)) \ 232e9efe16dSYoshinori Sato __w = (__w & 0x00ff) | (__d << 8); \ 233e9efe16dSYoshinori Sato else \ 234e9efe16dSYoshinori Sato __w = (__w & 0xff00) | (__d); \ 235e9efe16dSYoshinori Sato SMC_outw((a), __w, ((r)&(~1))); \ 236e9efe16dSYoshinori Sato }) 237e9efe16dSYoshinori Sato #define SMC_outsw(a, r, b, l) \ 238e9efe16dSYoshinori Sato do { \ 239e9efe16dSYoshinori Sato int __i; \ 240e9efe16dSYoshinori Sato word *__b2 = (word *)(b); \ 241e9efe16dSYoshinori Sato for (__i = 0; __i < (l); __i++) { \ 242e9efe16dSYoshinori Sato SMC_outw(a, SWAB7206(*__b2), r); \ 243e9efe16dSYoshinori Sato __b2++; \ 244e9efe16dSYoshinori Sato } \ 245e9efe16dSYoshinori Sato } while (0) 246abc20abaSMarek Vasut #else /* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */ 2472439e4bfSJean-Christophe PLAGNIOL-VILLARD 2482439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */ 2492439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 2502439e4bfSJean-Christophe PLAGNIOL-VILLARD * We have only 16 Bit PCMCIA access on Socket 0 2512439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 2522439e4bfSJean-Christophe PLAGNIOL-VILLARD 2532439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_ADNPESC1 2547194ab80SBen Warren #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) 255ee456337SBhupesh Sharma #elif CONFIG_ARM64 256ee456337SBhupesh Sharma #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r))))) 2572439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 2587194ab80SBen Warren #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r)))) 2592439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 2607194ab80SBen Warren #define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF)) 2612439e4bfSJean-Christophe PLAGNIOL-VILLARD 2622439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_ADNPESC1 2637194ab80SBen Warren #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d) 264ee456337SBhupesh Sharma #elif CONFIG_ARM64 265ee456337SBhupesh Sharma #define SMC_outw(a, d, r) \ 266ee456337SBhupesh Sharma (*((volatile word*)((a)->iobase+((dword)(r)))) = d) 2672439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 268ee456337SBhupesh Sharma #define SMC_outw(a, d, r) \ 269ee456337SBhupesh Sharma (*((volatile word*)((a)->iobase+(r))) = d) 2702439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 2717194ab80SBen Warren #define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ 2727194ab80SBen Warren word __w = SMC_inw((a),(r)&~1); \ 2732439e4bfSJean-Christophe PLAGNIOL-VILLARD __w &= ((r)&1) ? 0x00FF : 0xFF00; \ 2742439e4bfSJean-Christophe PLAGNIOL-VILLARD __w |= ((r)&1) ? __d<<8 : __d; \ 2757194ab80SBen Warren SMC_outw((a),__w,(r)&~1); \ 2762439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 2772439e4bfSJean-Christophe PLAGNIOL-VILLARD #if 0 2787194ab80SBen Warren #define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l)) 2792439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 2807194ab80SBen Warren #define SMC_outsw(a,r,b,l) ({ int __i; \ 2812439e4bfSJean-Christophe PLAGNIOL-VILLARD word *__b2; \ 2822439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (word *) b; \ 2832439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 2847194ab80SBen Warren SMC_outw((a), *(__b2 + __i), r); \ 2852439e4bfSJean-Christophe PLAGNIOL-VILLARD } \ 2862439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 2872439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 2882439e4bfSJean-Christophe PLAGNIOL-VILLARD 2892439e4bfSJean-Christophe PLAGNIOL-VILLARD #if 0 2907194ab80SBen Warren #define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l)) 2912439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 2927194ab80SBen Warren #define SMC_insw(a,r,b,l) ({ int __i ; \ 2932439e4bfSJean-Christophe PLAGNIOL-VILLARD word *__b2; \ 2942439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (word *) b; \ 2952439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 2967194ab80SBen Warren *(__b2 + __i) = SMC_inw((a),(r)); \ 2977194ab80SBen Warren SMC_inw((a),0); \ 2982439e4bfSJean-Christophe PLAGNIOL-VILLARD }; \ 2992439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 3002439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 3012439e4bfSJean-Christophe PLAGNIOL-VILLARD 3022439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif /* CONFIG_SMC_USE_IOFUNCS */ 3032439e4bfSJean-Christophe PLAGNIOL-VILLARD 3042439e4bfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_SMC_USE_32_BIT) 3052439e4bfSJean-Christophe PLAGNIOL-VILLARD 3062439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_XSENGINE 3077194ab80SBen Warren #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1)))) 3082439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 3097194ab80SBen Warren #define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) 3102439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 3112439e4bfSJean-Christophe PLAGNIOL-VILLARD 3127194ab80SBen Warren #define SMC_insl(a,r,b,l) ({ int __i ; \ 3132439e4bfSJean-Christophe PLAGNIOL-VILLARD dword *__b2; \ 3142439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (dword *) b; \ 3152439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 3167194ab80SBen Warren *(__b2 + __i) = SMC_inl((a),(r)); \ 3177194ab80SBen Warren SMC_inl((a),0); \ 3182439e4bfSJean-Christophe PLAGNIOL-VILLARD }; \ 3192439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 3202439e4bfSJean-Christophe PLAGNIOL-VILLARD 3212439e4bfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_XSENGINE 3227194ab80SBen Warren #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) 3232439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 3247194ab80SBen Warren #define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) 3252439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 3267194ab80SBen Warren #define SMC_outsl(a,r,b,l) ({ int __i; \ 3272439e4bfSJean-Christophe PLAGNIOL-VILLARD dword *__b2; \ 3282439e4bfSJean-Christophe PLAGNIOL-VILLARD __b2 = (dword *) b; \ 3292439e4bfSJean-Christophe PLAGNIOL-VILLARD for (__i = 0; __i < l; __i++) { \ 3307194ab80SBen Warren SMC_outl((a), *(__b2 + __i), r); \ 3312439e4bfSJean-Christophe PLAGNIOL-VILLARD } \ 3322439e4bfSJean-Christophe PLAGNIOL-VILLARD }) 3332439e4bfSJean-Christophe PLAGNIOL-VILLARD 3342439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif /* CONFIG_SMC_USE_32_BIT */ 3352439e4bfSJean-Christophe PLAGNIOL-VILLARD 3362439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 3372439e4bfSJean-Christophe PLAGNIOL-VILLARD 3382439e4bfSJean-Christophe PLAGNIOL-VILLARD /*--------------------------------------------------------------- 3392439e4bfSJean-Christophe PLAGNIOL-VILLARD . 3402439e4bfSJean-Christophe PLAGNIOL-VILLARD . A description of the SMSC registers is probably in order here, 3412439e4bfSJean-Christophe PLAGNIOL-VILLARD . although for details, the SMC datasheet is invaluable. 3422439e4bfSJean-Christophe PLAGNIOL-VILLARD . 3432439e4bfSJean-Christophe PLAGNIOL-VILLARD . Basically, the chip has 4 banks of registers ( 0 to 3 ), which 3442439e4bfSJean-Christophe PLAGNIOL-VILLARD . are accessed by writing a number into the BANK_SELECT register 3452439e4bfSJean-Christophe PLAGNIOL-VILLARD . ( I also use a SMC_SELECT_BANK macro for this ). 3462439e4bfSJean-Christophe PLAGNIOL-VILLARD . 3472439e4bfSJean-Christophe PLAGNIOL-VILLARD . The banks are configured so that for most purposes, bank 2 is all 3482439e4bfSJean-Christophe PLAGNIOL-VILLARD . that is needed for simple run time tasks. 3492439e4bfSJean-Christophe PLAGNIOL-VILLARD -----------------------------------------------------------------------*/ 3502439e4bfSJean-Christophe PLAGNIOL-VILLARD 3512439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 3522439e4bfSJean-Christophe PLAGNIOL-VILLARD . Bank Select Register: 3532439e4bfSJean-Christophe PLAGNIOL-VILLARD . 3542439e4bfSJean-Christophe PLAGNIOL-VILLARD . yyyy yyyy 0000 00xx 3552439e4bfSJean-Christophe PLAGNIOL-VILLARD . xx = bank number 3562439e4bfSJean-Christophe PLAGNIOL-VILLARD . yyyy yyyy = 0x33, for identification purposes. 3572439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 3582439e4bfSJean-Christophe PLAGNIOL-VILLARD #define BANK_SELECT 14 3592439e4bfSJean-Christophe PLAGNIOL-VILLARD 3602439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Transmit Control Register */ 3612439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 0 */ 3622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_REG 0x0000 /* transmit control register */ 3632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_ENABLE 0x0001 /* When 1 we can transmit */ 3642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_LOOP 0x0002 /* Controls output pin LBK */ 3652439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_FORCOL 0x0004 /* When 1 will force a collision */ 3662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_PAD_EN 0x0080 /* When 1 will pad tx frames < 64 bytes w/0 */ 3672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_NOCRC 0x0100 /* When 1 will not append CRC to tx frames */ 3682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_MON_CSN 0x0400 /* When 1 tx monitors carrier */ 3692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_FDUPLX 0x0800 /* When 1 enables full duplex operation */ 3702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_STP_SQET 0x1000 /* When 1 stops tx if Signal Quality Error */ 3712439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_EPH_LOOP 0x2000 /* When 1 enables EPH block loopback */ 3722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_SWFDUP 0x8000 /* When 1 enables Switched Full Duplex mode */ 3732439e4bfSJean-Christophe PLAGNIOL-VILLARD 3742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_CLEAR 0 /* do NOTHING */ 3752439e4bfSJean-Christophe PLAGNIOL-VILLARD /* the default settings for the TCR register : */ 3762439e4bfSJean-Christophe PLAGNIOL-VILLARD /* QUESTION: do I want to enable padding of short packets ? */ 3772439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TCR_DEFAULT TCR_ENABLE 3782439e4bfSJean-Christophe PLAGNIOL-VILLARD 3792439e4bfSJean-Christophe PLAGNIOL-VILLARD 3802439e4bfSJean-Christophe PLAGNIOL-VILLARD /* EPH Status Register */ 3812439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 0 */ 3822439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EPH_STATUS_REG 0x0002 3832439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_TX_SUC 0x0001 /* Last TX was successful */ 3842439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_SNGL_COL 0x0002 /* Single collision detected for last tx */ 3852439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_MUL_COL 0x0004 /* Multiple collisions detected for last tx */ 3862439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_LTX_MULT 0x0008 /* Last tx was a multicast */ 3872439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_16COL 0x0010 /* 16 Collisions Reached */ 3882439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_SQET 0x0020 /* Signal Quality Error Test */ 3892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_LTXBRD 0x0040 /* Last tx was a broadcast */ 3902439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_TXDEFR 0x0080 /* Transmit Deferred */ 3912439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_LATCOL 0x0200 /* Late collision detected on last tx */ 3922439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_LOSTCARR 0x0400 /* Lost Carrier Sense */ 3932439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_EXC_DEF 0x0800 /* Excessive Deferral */ 3942439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_CTR_ROL 0x1000 /* Counter Roll Over indication */ 3952439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_LINK_OK 0x4000 /* Driven by inverted value of nLNK pin */ 3962439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ES_TXUNRN 0x8000 /* Tx Underrun */ 3972439e4bfSJean-Christophe PLAGNIOL-VILLARD 3982439e4bfSJean-Christophe PLAGNIOL-VILLARD 3992439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Receive Control Register */ 4002439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 0 */ 4012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_REG 0x0004 4022439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_RX_ABORT 0x0001 /* Set if a rx frame was aborted */ 4032439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_PRMS 0x0002 /* Enable promiscuous mode */ 4042439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_ALMUL 0x0004 /* When set accepts all multicast frames */ 4052439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_RXEN 0x0100 /* IFF this is set, we can receive packets */ 4062439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_STRIP_CRC 0x0200 /* When set strips CRC from rx packets */ 4072439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_ABORT_ENB 0x0200 /* When set will abort rx on collision */ 4082439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_FILT_CAR 0x0400 /* When set filters leading 12 bit s of carrier */ 4092439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_SOFTRST 0x8000 /* resets the chip */ 4102439e4bfSJean-Christophe PLAGNIOL-VILLARD 4112439e4bfSJean-Christophe PLAGNIOL-VILLARD /* the normal settings for the RCR register : */ 4122439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) 4132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RCR_CLEAR 0x0 /* set it to a base state */ 4142439e4bfSJean-Christophe PLAGNIOL-VILLARD 4152439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Counter Register */ 4162439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 0 */ 4172439e4bfSJean-Christophe PLAGNIOL-VILLARD #define COUNTER_REG 0x0006 4182439e4bfSJean-Christophe PLAGNIOL-VILLARD 4192439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Memory Information Register */ 4202439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 0 */ 4212439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MIR_REG 0x0008 4222439e4bfSJean-Christophe PLAGNIOL-VILLARD 4232439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Receive/Phy Control Register */ 4242439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 0 */ 4252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_REG 0x000A 4262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_SPEED 0x2000 /* When 1 PHY is in 100Mbps mode. */ 4272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_DPLX 0x1000 /* When 1 PHY is in Full-Duplex Mode */ 4282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_ANEG 0x0800 /* When 1 PHY is in Auto-Negotiate Mode */ 4292439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LSXA_SHFT 5 /* Bits to shift LS2A,LS1A,LS0A to lsb */ 4302439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LSXB_SHFT 2 /* Bits to get LS2B,LS1B,LS0B to lsb */ 4312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_100_10 (0x00) /* LED = 100Mbps OR's with 10Mbps link detect */ 4322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_RES (0x01) /* LED = Reserved */ 4332439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_10 (0x02) /* LED = 10Mbps link detect */ 4342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_FD (0x03) /* LED = Full Duplex Mode */ 4352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_TX_RX (0x04) /* LED = TX or RX packet occurred */ 4362439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */ 4372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_TX (0x06) /* LED = TX packet occurred */ 4382439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_LED_RX (0x07) /* LED = RX packet occurred */ 4392439e4bfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10) 4402439e4bfSJean-Christophe PLAGNIOL-VILLARD /* buggy schematic: LEDa -> yellow, LEDb --> green */ 4412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ 4422439e4bfSJean-Christophe PLAGNIOL-VILLARD | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ 4432439e4bfSJean-Christophe PLAGNIOL-VILLARD | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) 4442439e4bfSJean-Christophe PLAGNIOL-VILLARD #elif defined(CONFIG_ADNPESC1) 4452439e4bfSJean-Christophe PLAGNIOL-VILLARD /* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */ 4462439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ 4472439e4bfSJean-Christophe PLAGNIOL-VILLARD | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ 4482439e4bfSJean-Christophe PLAGNIOL-VILLARD | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) 4492439e4bfSJean-Christophe PLAGNIOL-VILLARD #else 4502439e4bfSJean-Christophe PLAGNIOL-VILLARD /* SMSC reference design: LEDa --> green, LEDb --> yellow */ 4512439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ 4522439e4bfSJean-Christophe PLAGNIOL-VILLARD | (RPC_LED_100_10 << RPC_LSXA_SHFT) \ 4532439e4bfSJean-Christophe PLAGNIOL-VILLARD | (RPC_LED_TX_RX << RPC_LSXB_SHFT) ) 4542439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 4552439e4bfSJean-Christophe PLAGNIOL-VILLARD 4562439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Bank 0 0x000C is reserved */ 4572439e4bfSJean-Christophe PLAGNIOL-VILLARD 4582439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Bank Select Register */ 4592439e4bfSJean-Christophe PLAGNIOL-VILLARD /* All Banks */ 4602439e4bfSJean-Christophe PLAGNIOL-VILLARD #define BSR_REG 0x000E 4612439e4bfSJean-Christophe PLAGNIOL-VILLARD 4622439e4bfSJean-Christophe PLAGNIOL-VILLARD 4632439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Configuration Reg */ 4642439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 1 */ 4652439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_REG 0x0000 4662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_EXT_PHY 0x0200 /* 1=external MII, 0=internal Phy */ 4672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_GPCNTRL 0x0400 /* Inverse value drives pin nCNTRL */ 4682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_NO_WAIT 0x1000 /* When 1 no extra wait states on ISA bus */ 4692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_EPH_POWER_EN 0x8000 /* When 0 EPH is placed into low power mode. */ 4702439e4bfSJean-Christophe PLAGNIOL-VILLARD 4712439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low */ 4722439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) 4732439e4bfSJean-Christophe PLAGNIOL-VILLARD 4742439e4bfSJean-Christophe PLAGNIOL-VILLARD 4752439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Base Address Register */ 4762439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 1 */ 4772439e4bfSJean-Christophe PLAGNIOL-VILLARD #define BASE_REG 0x0002 4782439e4bfSJean-Christophe PLAGNIOL-VILLARD 4792439e4bfSJean-Christophe PLAGNIOL-VILLARD 4802439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Individual Address Registers */ 4812439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 1 */ 4822439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ADDR0_REG 0x0004 4832439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ADDR1_REG 0x0006 4842439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ADDR2_REG 0x0008 4852439e4bfSJean-Christophe PLAGNIOL-VILLARD 4862439e4bfSJean-Christophe PLAGNIOL-VILLARD 4872439e4bfSJean-Christophe PLAGNIOL-VILLARD /* General Purpose Register */ 4882439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 1 */ 4892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define GP_REG 0x000A 4902439e4bfSJean-Christophe PLAGNIOL-VILLARD 4912439e4bfSJean-Christophe PLAGNIOL-VILLARD 4922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Control Register */ 4932439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 1 */ 4942439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_REG 0x000C 4952439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_RCV_BAD 0x4000 /* When 1 bad CRC packets are received */ 4962439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_AUTO_RELEASE 0x0800 /* When 1 tx pages are released automatically */ 4972439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_LE_ENABLE 0x0080 /* When 1 enables Link Error interrupt */ 4982439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_CR_ENABLE 0x0040 /* When 1 enables Counter Rollover interrupt */ 4992439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_TE_ENABLE 0x0020 /* When 1 enables Transmit Error interrupt */ 5002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_EEPROM_SELECT 0x0004 /* Controls EEPROM reload & store */ 5012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_RELOAD 0x0002 /* When set reads EEPROM into registers */ 5022439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_STORE 0x0001 /* When set stores registers into EEPROM */ 5032439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CTL_DEFAULT (0x1A10) /* Autorelease enabled*/ 5042439e4bfSJean-Christophe PLAGNIOL-VILLARD 5052439e4bfSJean-Christophe PLAGNIOL-VILLARD /* MMU Command Register */ 5062439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 5072439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MMU_CMD_REG 0x0000 5082439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_BUSY 1 /* When 1 the last release has not completed */ 5092439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_NOP (0<<5) /* No Op */ 5102439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_ALLOC (1<<5) /* OR with number of 256 byte packets */ 5112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_RESET (2<<5) /* Reset MMU to initial state */ 5122439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_REMOVE (3<<5) /* Remove the current rx packet */ 5132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_RELEASE (4<<5) /* Remove and release the current rx packet */ 5142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_FREEPKT (5<<5) /* Release packet in PNR register */ 5152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_ENQUEUE (6<<5) /* Enqueue the packet for transmit */ 5162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MC_RSTTXFIFO (7<<5) /* Reset the TX FIFOs */ 5172439e4bfSJean-Christophe PLAGNIOL-VILLARD 5182439e4bfSJean-Christophe PLAGNIOL-VILLARD 5192439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Packet Number Register */ 5202439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 5212439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PN_REG 0x0002 5222439e4bfSJean-Christophe PLAGNIOL-VILLARD 5232439e4bfSJean-Christophe PLAGNIOL-VILLARD 5242439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Allocation Result Register */ 5252439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 5262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define AR_REG 0x0003 5272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define AR_FAILED 0x80 /* Alocation Failed */ 5282439e4bfSJean-Christophe PLAGNIOL-VILLARD 5292439e4bfSJean-Christophe PLAGNIOL-VILLARD 5302439e4bfSJean-Christophe PLAGNIOL-VILLARD /* RX FIFO Ports Register */ 5312439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 5322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RXFIFO_REG 0x0004 /* Must be read as a word */ 5332439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RXFIFO_REMPTY 0x8000 /* RX FIFO Empty */ 5342439e4bfSJean-Christophe PLAGNIOL-VILLARD 5352439e4bfSJean-Christophe PLAGNIOL-VILLARD 5362439e4bfSJean-Christophe PLAGNIOL-VILLARD /* TX FIFO Ports Register */ 5372439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 5382439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TXFIFO_REG RXFIFO_REG /* Must be read as a word */ 5392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TXFIFO_TEMPTY 0x80 /* TX FIFO Empty */ 5402439e4bfSJean-Christophe PLAGNIOL-VILLARD 5412439e4bfSJean-Christophe PLAGNIOL-VILLARD 5422439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Pointer Register */ 5432439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 5442439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PTR_REG 0x0006 5452439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PTR_RCV 0x8000 /* 1=Receive area, 0=Transmit area */ 5462439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PTR_AUTOINC 0x4000 /* Auto increment the pointer on each access */ 5472439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PTR_READ 0x2000 /* When 1 the operation is a read */ 5482439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PTR_NOTEMPTY 0x0800 /* When 1 _do not_ write fifo DATA REG */ 5492439e4bfSJean-Christophe PLAGNIOL-VILLARD 5502439e4bfSJean-Christophe PLAGNIOL-VILLARD 5512439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Data Register */ 5522439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 5532439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC91111_DATA_REG 0x0008 5542439e4bfSJean-Christophe PLAGNIOL-VILLARD 5552439e4bfSJean-Christophe PLAGNIOL-VILLARD 5562439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Interrupt Status/Acknowledge Register */ 5572439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 5582439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC91111_INT_REG 0x000C 5592439e4bfSJean-Christophe PLAGNIOL-VILLARD 5602439e4bfSJean-Christophe PLAGNIOL-VILLARD 5612439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Interrupt Mask Register */ 5622439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 2 */ 5632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_REG 0x000D 5642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_MDINT 0x80 /* PHY MI Register 18 Interrupt */ 5652439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_ERCV_INT 0x40 /* Early Receive Interrupt */ 5662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_EPH_INT 0x20 /* Set by Etheret Protocol Handler section */ 5672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_RX_OVRN_INT 0x10 /* Set by Receiver Overruns */ 5682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_ALLOC_INT 0x08 /* Set when allocation request is completed */ 5692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_TX_EMPTY_INT 0x04 /* Set if the TX FIFO goes empty */ 5702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_TX_INT 0x02 /* Transmit Interrrupt */ 5712439e4bfSJean-Christophe PLAGNIOL-VILLARD #define IM_RCV_INT 0x01 /* Receive Interrupt */ 5722439e4bfSJean-Christophe PLAGNIOL-VILLARD 5732439e4bfSJean-Christophe PLAGNIOL-VILLARD 5742439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Multicast Table Registers */ 5752439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 3 */ 5762439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MCAST_REG1 0x0000 5772439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MCAST_REG2 0x0002 5782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MCAST_REG3 0x0004 5792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MCAST_REG4 0x0006 5802439e4bfSJean-Christophe PLAGNIOL-VILLARD 5812439e4bfSJean-Christophe PLAGNIOL-VILLARD 5822439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Management Interface Register (MII) */ 5832439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 3 */ 5842439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_REG 0x0008 5852439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_MSK_CRS100 0x4000 /* Disables CRS100 detection during tx half dup */ 5862439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_MDOE 0x0008 /* MII Output Enable */ 5872439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_MCLK 0x0004 /* MII Clock, pin MDCLK */ 5882439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_MDI 0x0002 /* MII Input, pin MDI */ 5892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define MII_MDO 0x0001 /* MII Output, pin MDO */ 5902439e4bfSJean-Christophe PLAGNIOL-VILLARD 5912439e4bfSJean-Christophe PLAGNIOL-VILLARD 5922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Revision Register */ 5932439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 3 */ 5942439e4bfSJean-Christophe PLAGNIOL-VILLARD #define REV_REG 0x000A /* ( hi: chip id low: rev # ) */ 5952439e4bfSJean-Christophe PLAGNIOL-VILLARD 5962439e4bfSJean-Christophe PLAGNIOL-VILLARD 5972439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Early RCV Register */ 5982439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 3 */ 5992439e4bfSJean-Christophe PLAGNIOL-VILLARD /* this is NOT on SMC9192 */ 6002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ERCV_REG 0x000C 6012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ERCV_RCV_DISCRD 0x0080 /* When 1 discards a packet being received */ 6022439e4bfSJean-Christophe PLAGNIOL-VILLARD #define ERCV_THRESHOLD 0x001F /* ERCV Threshold Mask */ 6032439e4bfSJean-Christophe PLAGNIOL-VILLARD 6042439e4bfSJean-Christophe PLAGNIOL-VILLARD /* External Register */ 6052439e4bfSJean-Christophe PLAGNIOL-VILLARD /* BANK 7 */ 6062439e4bfSJean-Christophe PLAGNIOL-VILLARD #define EXT_REG 0x0000 6072439e4bfSJean-Christophe PLAGNIOL-VILLARD 6082439e4bfSJean-Christophe PLAGNIOL-VILLARD 6092439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CHIP_9192 3 6102439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CHIP_9194 4 6112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CHIP_9195 5 6122439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CHIP_9196 6 6132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CHIP_91100 7 6142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CHIP_91100FD 8 6152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define CHIP_91111FD 9 6162439e4bfSJean-Christophe PLAGNIOL-VILLARD 6172439e4bfSJean-Christophe PLAGNIOL-VILLARD #if 0 6182439e4bfSJean-Christophe PLAGNIOL-VILLARD static const char * chip_ids[ 15 ] = { 6192439e4bfSJean-Christophe PLAGNIOL-VILLARD NULL, NULL, NULL, 6202439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 3 */ "SMC91C90/91C92", 6212439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 4 */ "SMC91C94", 6222439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 5 */ "SMC91C95", 6232439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 6 */ "SMC91C96", 6242439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 7 */ "SMC91C100", 6252439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 8 */ "SMC91C100FD", 6262439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 9 */ "SMC91C111", 6272439e4bfSJean-Christophe PLAGNIOL-VILLARD NULL, NULL, 6282439e4bfSJean-Christophe PLAGNIOL-VILLARD NULL, NULL, NULL}; 6292439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif 6302439e4bfSJean-Christophe PLAGNIOL-VILLARD 6312439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 6322439e4bfSJean-Christophe PLAGNIOL-VILLARD . Transmit status bits 6332439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 6342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TS_SUCCESS 0x0001 6352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TS_LOSTCAR 0x0400 6362439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TS_LATCOL 0x0200 6372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define TS_16COL 0x0010 6382439e4bfSJean-Christophe PLAGNIOL-VILLARD 6392439e4bfSJean-Christophe PLAGNIOL-VILLARD /* 6402439e4bfSJean-Christophe PLAGNIOL-VILLARD . Receive status bits 6412439e4bfSJean-Christophe PLAGNIOL-VILLARD */ 6422439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_ALGNERR 0x8000 6432439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_BRODCAST 0x4000 6442439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_BADCRC 0x2000 6452439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_ODDFRAME 0x1000 /* bug: the LAN91C111 never sets this on receive */ 6462439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_TOOLONG 0x0800 6472439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_TOOSHORT 0x0400 6482439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_MULTICAST 0x0001 6492439e4bfSJean-Christophe PLAGNIOL-VILLARD #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 6502439e4bfSJean-Christophe PLAGNIOL-VILLARD 6512439e4bfSJean-Christophe PLAGNIOL-VILLARD 6522439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Types */ 6532439e4bfSJean-Christophe PLAGNIOL-VILLARD enum { 6542439e4bfSJean-Christophe PLAGNIOL-VILLARD PHY_LAN83C183 = 1, /* LAN91C111 Internal PHY */ 6552439e4bfSJean-Christophe PLAGNIOL-VILLARD PHY_LAN83C180 6562439e4bfSJean-Christophe PLAGNIOL-VILLARD }; 6572439e4bfSJean-Christophe PLAGNIOL-VILLARD 6582439e4bfSJean-Christophe PLAGNIOL-VILLARD 6592439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Register Addresses (LAN91C111 Internal PHY) */ 6602439e4bfSJean-Christophe PLAGNIOL-VILLARD 6612439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Control Register */ 6622439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_REG 0x00 6632439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ 6642439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ 6652439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ 6662439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ 6672439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ 6682439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ 6692439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ 6702439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ 6712439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ 6722439e4bfSJean-Christophe PLAGNIOL-VILLARD 6732439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Status Register */ 6742439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_REG 0x01 6752439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ 6762439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ 6772439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ 6782439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ 6792439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ 6802439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ 6812439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ 6822439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ 6832439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ 6842439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_LINK 0x0004 /* 1=valid link */ 6852439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ 6862439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ 6872439e4bfSJean-Christophe PLAGNIOL-VILLARD 6882439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Identifier Registers */ 6892439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ 6902439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ 6912439e4bfSJean-Christophe PLAGNIOL-VILLARD 6922439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Auto-Negotiation Advertisement Register */ 6932439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_REG 0x04 6942439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ 6952439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ 6962439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ 6972439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ 6982439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ 6992439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ 7002439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ 7012439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ 7022439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ 7032439e4bfSJean-Christophe PLAGNIOL-VILLARD 7042439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Auto-negotiation Remote End Capability Register */ 7052439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_RMT_REG 0x05 7062439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Uses same bit definitions as PHY_AD_REG */ 7072439e4bfSJean-Christophe PLAGNIOL-VILLARD 7082439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Configuration Register 1 */ 7092439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_REG 0x10 7102439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ 7112439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ 7122439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ 7132439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ 7142439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ 7152439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ 7162439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ 7172439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ 7182439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ 7192439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_TLVL_MASK 0x003C 7202439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ 7212439e4bfSJean-Christophe PLAGNIOL-VILLARD 7222439e4bfSJean-Christophe PLAGNIOL-VILLARD 7232439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Configuration Register 2 */ 7242439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG2_REG 0x11 7252439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ 7262439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ 7272439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ 7282439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ 7292439e4bfSJean-Christophe PLAGNIOL-VILLARD 7302439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Status Output (and Interrupt status) Register */ 7312439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ 7322439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ 7332439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ 7342439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ 7352439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ 7362439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ 7372439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ 7382439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ 7392439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ 7402439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ 7412439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ 7422439e4bfSJean-Christophe PLAGNIOL-VILLARD 7432439e4bfSJean-Christophe PLAGNIOL-VILLARD /* PHY Interrupt/Status Mask Register */ 7442439e4bfSJean-Christophe PLAGNIOL-VILLARD #define PHY_MASK_REG 0x13 /* Interrupt Mask */ 7452439e4bfSJean-Christophe PLAGNIOL-VILLARD /* Uses the same bit definitions as PHY_INT_REG */ 7462439e4bfSJean-Christophe PLAGNIOL-VILLARD 7472439e4bfSJean-Christophe PLAGNIOL-VILLARD 7482439e4bfSJean-Christophe PLAGNIOL-VILLARD /*------------------------------------------------------------------------- 7492439e4bfSJean-Christophe PLAGNIOL-VILLARD . I define some macros to make it easier to do somewhat common 7502439e4bfSJean-Christophe PLAGNIOL-VILLARD . or slightly complicated, repeated tasks. 7512439e4bfSJean-Christophe PLAGNIOL-VILLARD --------------------------------------------------------------------------*/ 7522439e4bfSJean-Christophe PLAGNIOL-VILLARD 7532439e4bfSJean-Christophe PLAGNIOL-VILLARD /* select a register bank, 0 to 3 */ 7542439e4bfSJean-Christophe PLAGNIOL-VILLARD 7557194ab80SBen Warren #define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); } 7562439e4bfSJean-Christophe PLAGNIOL-VILLARD 7572439e4bfSJean-Christophe PLAGNIOL-VILLARD /* this enables an interrupt in the interrupt mask register */ 7587194ab80SBen Warren #define SMC_ENABLE_INT(a,x) {\ 7592439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned char mask;\ 7607194ab80SBen Warren SMC_SELECT_BANK((a),2);\ 7617194ab80SBen Warren mask = SMC_inb((a), IM_REG );\ 7622439e4bfSJean-Christophe PLAGNIOL-VILLARD mask |= (x);\ 7637194ab80SBen Warren SMC_outb( (a), mask, IM_REG ); \ 7642439e4bfSJean-Christophe PLAGNIOL-VILLARD } 7652439e4bfSJean-Christophe PLAGNIOL-VILLARD 7662439e4bfSJean-Christophe PLAGNIOL-VILLARD /* this disables an interrupt from the interrupt mask register */ 7672439e4bfSJean-Christophe PLAGNIOL-VILLARD 7687194ab80SBen Warren #define SMC_DISABLE_INT(a,x) {\ 7692439e4bfSJean-Christophe PLAGNIOL-VILLARD unsigned char mask;\ 7702439e4bfSJean-Christophe PLAGNIOL-VILLARD SMC_SELECT_BANK(2);\ 7717194ab80SBen Warren mask = SMC_inb( (a), IM_REG );\ 7722439e4bfSJean-Christophe PLAGNIOL-VILLARD mask &= ~(x);\ 7737194ab80SBen Warren SMC_outb( (a), mask, IM_REG ); \ 7742439e4bfSJean-Christophe PLAGNIOL-VILLARD } 7752439e4bfSJean-Christophe PLAGNIOL-VILLARD 7762439e4bfSJean-Christophe PLAGNIOL-VILLARD /*---------------------------------------------------------------------- 7772439e4bfSJean-Christophe PLAGNIOL-VILLARD . Define the interrupts that I want to receive from the card 7782439e4bfSJean-Christophe PLAGNIOL-VILLARD . 7792439e4bfSJean-Christophe PLAGNIOL-VILLARD . I want: 7802439e4bfSJean-Christophe PLAGNIOL-VILLARD . IM_EPH_INT, for nasty errors 7812439e4bfSJean-Christophe PLAGNIOL-VILLARD . IM_RCV_INT, for happy received packets 7822439e4bfSJean-Christophe PLAGNIOL-VILLARD . IM_RX_OVRN_INT, because I have to kick the receiver 7832439e4bfSJean-Christophe PLAGNIOL-VILLARD . IM_MDINT, for PHY Register 18 Status Changes 7842439e4bfSJean-Christophe PLAGNIOL-VILLARD --------------------------------------------------------------------------*/ 7852439e4bfSJean-Christophe PLAGNIOL-VILLARD #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \ 7862439e4bfSJean-Christophe PLAGNIOL-VILLARD IM_MDINT) 7872439e4bfSJean-Christophe PLAGNIOL-VILLARD 7882439e4bfSJean-Christophe PLAGNIOL-VILLARD #endif /* _SMC_91111_H_ */ 789