#
34aee9c9 |
| 08-Nov-2023 |
Thomas Huth <thuth@redhat.com> |
host/include/generic/host/atomic128: Fix compilation problem with Clang 17
When compiling QEMU with Clang 17 on a s390x, the compilation fails:
In file included from ../accel/tcg/cputlb.c:32: In fi
host/include/generic/host/atomic128: Fix compilation problem with Clang 17
When compiling QEMU with Clang 17 on a s390x, the compilation fails:
In file included from ../accel/tcg/cputlb.c:32: In file included from /root/qemu/include/exec/helper-proto-common.h:10: In file included from /root/qemu/include/qemu/atomic128.h:62: /root/qemu/host/include/generic/host/atomic128-ldst.h:68:15: error: __sync builtin operation MUST have natural alignment (consider using __ atomic). [-Werror,-Wsync-alignment] 68 | } while (!__sync_bool_compare_and_swap_16(ptr_align, old, new.i)); | ^ In file included from ../accel/tcg/cputlb.c:32: In file included from /root/qemu/include/exec/helper-proto-common.h:10: In file included from /root/qemu/include/qemu/atomic128.h:61: /root/qemu/host/include/generic/host/atomic128-cas.h:36:11: error: __sync builtin operation MUST have natural alignment (consider using __a tomic). [-Werror,-Wsync-alignment] 36 | r.i = __sync_val_compare_and_swap_16(ptr_align, c.i, n.i); | ^ 2 errors generated.
It's arguably a bug in Clang since we already use __builtin_assume_aligned() to tell the compiler that the pointer is properly aligned. But according to https://github.com/llvm/llvm-project/issues/69146 it seems like the Clang folks don't see an easy fix on their side and recommend to use a type declared with __attribute__((aligned(16))) to work around this problem.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1934 Message-ID: <20231108085954.313071-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
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#
6479dd74 |
| 24-May-2023 |
Richard Henderson <richard.henderson@linaro.org> |
meson: Split test for __int128_t type from __int128_t arithmetic
Older versions of clang have missing runtime functions for arithmetic with -fsanitize=undefined (see 464e3671f9d5c), so we cannot use
meson: Split test for __int128_t type from __int128_t arithmetic
Older versions of clang have missing runtime functions for arithmetic with -fsanitize=undefined (see 464e3671f9d5c), so we cannot use __int128_t for implementing Int128. But __int128_t is present, data movement works, and it can be used for atomic128.
Probe for both CONFIG_INT128_TYPE and CONFIG_INT128, adjust qemu/int128.h to define Int128Alias if CONFIG_INT128_TYPE, and adjust the meson probe for atomics to use has_int128_type.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
c4075353 |
| 01-May-2023 |
Richard Henderson <richard.henderson@linaro.org> |
qemu/int128: Re-shuffle Int128Alias members
Clang 14, with --enable-tcg-interpreter errors with
include/qemu/int128.h:487:16: error: alignment of field 'i' (128 bits) does not match the alignment
qemu/int128: Re-shuffle Int128Alias members
Clang 14, with --enable-tcg-interpreter errors with
include/qemu/int128.h:487:16: error: alignment of field 'i' (128 bits) does not match the alignment of the first field in transparent union; transparent_union attribute ignored [-Werror,-Wignored-attributes] __int128_t i; ^ include/qemu/int128.h:486:12: note: alignment of first field is 64 bits Int128 s; ^ 1 error generated.
By placing the __uint128_t member first, this is avoided.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230501204625.277361-1-richard.henderson@linaro.org>
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Revision tags: v8.0.0, v7.2.0 |
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#
b959822c |
| 16-Oct-2022 |
Richard Henderson <richard.henderson@linaro.org> |
include/qemu/int128: Use Int128 structure for TCI
We are about to allow passing Int128 to/from tcg helper functions, but libffi doesn't support __int128_t, so use the structure.
In order for atomic
include/qemu/int128: Use Int128 structure for TCI
We are about to allow passing Int128 to/from tcg helper functions, but libffi doesn't support __int128_t, so use the structure.
In order for atomic128.h to continue working, we must provide a mechanism to frob between real __int128_t and the structure. Provide a new union, Int128Alias, for this. We cannot modify Int128 itself, as any changed alignment would also break libffi.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
4724bbd2 |
| 25-May-2022 |
Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> |
host-utils: Implemented unsigned 256-by-128 division
Based on already existing QEMU implementation, created an unsigned 256 bit by 128 bit division needed to implement the vector divide extended uns
host-utils: Implemented unsigned 256-by-128 division
Based on already existing QEMU implementation, created an unsigned 256 bit by 128 bit division needed to implement the vector divide extended unsigned instruction from PowerISA3.1
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220525134954.85056-5-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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Revision tags: v7.0.0 |
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#
bea59230 |
| 30-Mar-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
softfloat: add float128_to_int128
Implements float128_to_int128 based on parts_float_to_int logic.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richa
softfloat: add float128_to_int128
Implements float128_to_int128 based on parts_float_to_int logic.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220330175932.6995-7-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
613cf0fc |
| 30-Mar-2022 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
qemu/int128: add int128_urshift
Implement an unsigned right shift for Int128 values and add the same tests cases of int128_rshift in the unit test.
Signed-off-by: Matheus Ferst <matheus.ferst@eldor
qemu/int128: add int128_urshift
Implement an unsigned right shift for Int128 values and add the same tests cases of int128_rshift in the unit test.
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220330175932.6995-3-matheus.ferst@eldorado.org.br> [danielhb: fixed long lines in test_urshift()] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
e03b5686 |
| 23-Mar-2022 |
Marc-André Lureau <marcandre.lureau@redhat.com> |
Replace config-time define HOST_WORDS_BIGENDIAN
Replace a config-time define with a compile time condition define (compatible with clang and gcc) that must be declared prior to its usage. This avoid
Replace config-time define HOST_WORDS_BIGENDIAN
Replace a config-time define with a compile time condition define (compatible with clang and gcc) that must be declared prior to its usage. This avoids having a global configure time define, but also prevents from bad usage, if the config header wasn't included before.
This can help to make some code independent from qemu too.
gcc supports __BYTE_ORDER__ from about 4.6 and clang from 3.2.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> [ For the s390x parts I'm involved in ] Acked-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-7-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
e9d07601 |
| 06-Jan-2022 |
Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> |
qemu/int128: addition of div/rem 128-bit operations
Addition of div and rem on 128-bit integers, using the 128/64->128 divu and 64x64->128 mulu in host-utils. These operations will be used within di
qemu/int128: addition of div/rem 128-bit operations
Addition of div and rem on 128-bit integers, using the 128/64->128 divu and 64x64->128 mulu in host-utils. These operations will be used within div/rem helpers in the 128-bit riscv target.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-4-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v6.2.0 |
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#
1c469373 |
| 25-Oct-2021 |
Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> |
qemu/int128: Add int128_{not,xor}
Addition of not and xor on 128-bit integers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@g
qemu/int128: Add int128_{not,xor}
Addition of not and xor on 128-bit integers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Message-Id: <20211025122818.168890-3-frederic.petrot@univ-grenoble-alpes.fr> [rth: Split out logical operations.] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
2484cd9c |
| 26-Aug-2021 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
include/qemu/int128.h: introduce bswap128s
Changes the current bswap128 implementation to use __builtin_bswap128 when available, adds a bswap128 implementation for !CONFIG_INT128 builds, and introdu
include/qemu/int128.h: introduce bswap128s
Changes the current bswap128 implementation to use __builtin_bswap128 when available, adds a bswap128 implementation for !CONFIG_INT128 builds, and introduces bswap128s based on bswap128.
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210826145656.2507213-2-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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#
181b0c33 |
| 26-Aug-2021 |
Matheus Ferst <matheus.ferst@eldorado.org.br> |
include/qemu/int128.h: define struct Int128 according to the host endianness
Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by:
include/qemu/int128.h: define struct Int128 according to the host endianness
Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20210826141446.2488609-2-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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Revision tags: v6.1.0 |
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#
b22726ab |
| 22-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-6.1-pull-request' into staging Linux-user pull request 20210621 # gpg: Signature made Mon 21 Jun 2021 12:03:53 BST
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-6.1-pull-request' into staging Linux-user pull request 20210621 # gpg: Signature made Mon 21 Jun 2021 12:03:53 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-6.1-pull-request: linux-user: Use public sigev_notify_thread_id member if available linux-user: Fix incorrect use of feature-test-macros linux-user: Check for ieee128 fpbits in PPC64 HWCAP2 feature list tests/tcg/linux-test: Check that sigaction can query SIGKILL/SIGSTOP linux-user: Let sigaction query SIGKILL/SIGSTOP linux-user: Implement pivot_root linux-user/trace-events: fix minor typo in format string linux-user: Disable static assert involving __SIGRTMAX if it is missing linux-user: Set CF_PARALLEL when mapping shared memory Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
b6d73e9c |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging * avoid deprecation warnings for SASL on macOS 10.11 or newer * fix -readconfig when config blocks ha
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging * avoid deprecation warnings for SASL on macOS 10.11 or newer * fix -readconfig when config blocks have an id (like [chardev "qmp"]) * Error* initialization fixes * Improvements to ESP emulation (Mark) * Allow creating noreserve memory backends (David) * Improvements to query-memdev (David) * Bump compiler to C11 (Richard) * First round of SVM fixes from GSoC project (Lara) # gpg: Signature made Wed 16 Jun 2021 16:37:49 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: (45 commits) configure: Remove probe for _Static_assert qemu/compiler: Remove QEMU_GENERIC include/qemu/lockable: Use _Generic instead of QEMU_GENERIC util: Use unique type for QemuRecMutex in thread-posix.h util: Pass file+line to qemu_rec_mutex_unlock_impl util: Use real functions for thread-posix QemuRecMutex softfloat: Use _Generic instead of QEMU_GENERIC configure: Use -std=gnu11 target/i386: Added Intercept CR0 writes check target/i386: Added consistency checks for CR0 target/i386: Added consistency checks for VMRUN intercept and ASID target/i386: Refactored intercept checks into cpu_svm_has_intercept configure: map x32 to cpu_family x86_64 for meson hmp: Print "reserve" property of memory backends with "info memdev" qmp: Include "reserve" property of memory backends hmp: Print "share" property of memory backends with "info memdev" qmp: Include "share" property of memory backends qmp: Clarify memory backend properties returned via query-memdev hostmem: Wire up RAM_NORESERVE via "reserve" property util/mmap-alloc: Support RAM_NORESERVE via MAP_NORESERVE under Linux ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
18e53dff |
| 17-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-c11-20210615' into staging Change to -std=gnu11. Replace QEMU_GENERIC with _Generic. Remove configure detect of _Static_ass
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-c11-20210615' into staging Change to -std=gnu11. Replace QEMU_GENERIC with _Generic. Remove configure detect of _Static_assert. # gpg: Signature made Wed 16 Jun 2021 02:32:32 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-c11-20210615: configure: Remove probe for _Static_assert qemu/compiler: Remove QEMU_GENERIC include/qemu/lockable: Use _Generic instead of QEMU_GENERIC util: Use unique type for QemuRecMutex in thread-posix.h util: Pass file+line to qemu_rec_mutex_unlock_impl util: Use real functions for thread-posix QemuRecMutex softfloat: Use _Generic instead of QEMU_GENERIC configure: Use -std=gnu11 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
38848ce5 |
| 16-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210616' into staging target-arm queue: * hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes * handle some
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210616' into staging target-arm queue: * hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes * handle some UNALLOCATED decode cases correctly rather than asserting * hw: virt: consider hw_compat_6_0 * hw/arm: add quanta-gbs-bmc machine * hw/intc/armv7m_nvic: Remove stale comment * target/arm: Fix mte page crossing test * hw/arm: quanta-q71l add pca954x muxes * target/arm: First few parts of MVE support # gpg: Signature made Wed 16 Jun 2021 14:34:49 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210616: (25 commits) include/qemu/int128.h: Add function to create Int128 from int64_t bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations target/arm: Move expand_pred_b() data to vec_helper.c target/arm: Add framework for MVE decode target/arm: Implement MVE LETP insn target/arm: Implement MVE DLSTP target/arm: Implement MVE WLSTP insn target/arm: Implement MVE LCTP target/arm: Let vfp_access_check() handle late NOCP checks target/arm: Add handling for PSR.ECI/ICI target/arm: Handle VPR semantics in existing code target/arm: Enable FPSCR.QC bit for MVE target/arm: Provide and use H8 and H1_8 macros hw/arm: quanta-q71l add pca954x muxes hw/arm: gsj add pca9548 hw/arm: gsj add i2c comments target/arm: Fix mte page crossing test hw/intc/armv7m_nvic: Remove stale comment hw/arm: quanta-gbs-bmc add i2c comments hw/arm: add quanta-gbs-bmc machine ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
703235a3 |
| 14-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
include/qemu/int128.h: Add function to create Int128 from int64_t int128_make64() creates an Int128 from an unsigned 64 bit value; add a function int128_makes64() creating an Int128 from
include/qemu/int128.h: Add function to create Int128 from int64_t int128_make64() creates an Int128 from an unsigned 64 bit value; add a function int128_makes64() creating an Int128 from a signed 64 bit value. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210614151007.4545-34-peter.maydell@linaro.org
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#
e90ef023 |
| 19-Feb-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-02-18' into staging QAPI patches patches for 2021-02-18 # gpg: Signature made Thu 18 Feb 2021 18:51:35 GMT # gpg
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-02-18' into staging QAPI patches patches for 2021-02-18 # gpg: Signature made Thu 18 Feb 2021 18:51:35 GMT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2021-02-18: qapi/introspect.py: set _gen_tree's default ifcond argument to () qapi/introspect.py: Type _gen_tree variants as Sequence[str] qapi/introspect.py: Update copyright and authors list qapi/introspect.py: Add docstrings to _gen_tree and _tree_to_qlit qapi/introspect.py: add type hint annotations qapi/introspect.py: remove _gen_variants helper qapi/introspect.py: improve readability of _tree_to_qlit qapi/introspect.py: improve _tree_to_qlit error message qapi/introspect.py: create a typed 'Annotated' data strutcure qapi/introspect.py: Introduce preliminary tree typing qapi/introspect.py: Always define all 'extra' dict keys qapi/introspect.py: replace 'extra' dict with 'comment' argument qapi/introspect.py: Unify return type of _make_tree() qapi/introspect.py: guard against ifcond/comment misuse qapi/introspect.py: add _gen_features helper qapi/introspect.py: use _make_tree for features nodes qapi/introspect.py: assert schema is not None qapi: Replace List[str] with Sequence[str] for ifcond Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
c79f01c9 |
| 18-Feb-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210218' into staging Initial commit for the Qualcomm Hexagon processor. # gpg: Signature made Thu 18 Feb 2021 16:26:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210218' into staging Initial commit for the Qualcomm Hexagon processor. # gpg: Signature made Thu 18 Feb 2021 16:26:52 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-hex-20210218: (35 commits) Hexagon build infrastructure Hexagon (tests/tcg/hexagon) TCG tests - floating point Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc Hexagon (tests/tcg/hexagon) TCG tests - multiarch Hexagon (linux-user/hexagon) Linux user emulation Hexagon (target/hexagon) translation Hexagon (target/hexagon) TCG for floating point instructions Hexagon (target/hexagon) TCG for instructions with multiple definitions Hexagon (target/hexagon) TCG generation Hexagon (target/hexagon) instruction classes Hexagon (target/hexagon) macros Hexagon (target/hexagon) opcode data structures Hexagon (target/hexagon) generater phase 4 - decode tree Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree Hexagon (target/hexagon) generator phase 2 - generate header files Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics Hexagon (target/hexagon/imported) arch import Hexagon (target/hexagon/fma_emu.[ch]) utility functions Hexagon (target/hexagon/conv_emu.[ch]) utility functions Hexagon (target/hexagon/arch.[ch]) utility functions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v5.2.0 |
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#
08895cda |
| 20-Oct-2020 |
Richard Henderson <richard.henderson@linaro.org> |
qemu/int128: Add int128_or Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4
qemu/int128: Add int128_or Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20201021045149.1582203-2-richard.henderson@linaro.org>
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e4c4f7db |
| 07-Sep-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/hdeller/tags/target-hppa-pull-request' into staging hppa power button support, graphics updates and firmware fixes # gpg: Signature made Mon 07
Merge remote-tracking branch 'remotes/hdeller/tags/target-hppa-pull-request' into staging hppa power button support, graphics updates and firmware fixes # gpg: Signature made Mon 07 Sep 2020 20:09:49 BST # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * remotes/hdeller/tags/target-hppa-pull-request: hw/display/artist: Allow screen size up to 2048 lines hw/display/artist: Refactor x/y coordination extraction hw/display/artist: Verify artist screen resolution target/hppa: Fix boot with old Linux installation CDs hw/hppa: Add power button emulation hw/hppa: Tell SeaBIOS port address of fw_cfg hw/hppa: Change fw_cfg port address hw/hppa: Store boot device in fw_cfg section hw/hppa: Make number of TLB and BTLB entries configurable seabios-hppa: Update SeaBIOS to hppa-qemu-5.2-2 tag Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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39335fab |
| 28-Aug-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.2-pull-request' into staging add utimensat_time64, semtimedop_time64, rt_sigtimedwait_time64, sched_rr_get_interva
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.2-pull-request' into staging add utimensat_time64, semtimedop_time64, rt_sigtimedwait_time64, sched_rr_get_interval_time64, clock_nanosleep_time64, clock_adjtime64, mq_timedsend_time64, mq_timedreceive_time64 fix semop, semtimedop, clock_nanosleep, mq_timedsend, target_to_host_timespec64 fix tembits.h add more strace function Add upport DRM_IOCTL_I915_GETPARAM detect mismatched ELF ABI in qemu-mips[n32][el] # gpg: Signature made Fri 28 Aug 2020 14:37:33 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-5.2-pull-request: linux-user: Add support for utimensat_time64() and semtimedop_time64() linux-user: Add support for 'rt_sigtimedwait_time64()' and 'sched_rr_get_interval_time64()' linux-user: Add support for 'clock_nanosleep_time64()' and 'clock_adjtime64()' linux-user: Add support for 'mq_timedsend_time64()' and 'mq_timedreceive_time64()' linux-user: fix target_to_host_timespec64() linux-user: Fix 'mq_timedsend()' and 'mq_timedreceive()' linux-user: detect mismatched ELF ABI in qemu-mips[n32][el] linux-user: Add strace support for printing arguments for ioctls used for terminals and serial lines linux-user: Add missing termbits types and values definitions linux-user: Add generic 'termbits.h' for some archs linux-user: Add strace support for printing arguments of some clock and time functions linux-user: Add an api to print enumareted argument values with strace linux-user: Add strace support for printing arguments of syscalls used to lock and unlock memory linux-user: Add strace support for printing arguments of truncate()/ftruncate() and getsid() linux-user: Make cpu_env accessible in strace.c linux-user: syscall: ioctls: support DRM_IOCTL_I915_GETPARAM linux-user: Fix 'clock_nanosleep()' implementation linux-user: Fix 'semop()' and 'semtimedop()' implementation Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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a4e236b7 |
| 28-Aug-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20200828a' into staging Migration and virtiofsd pull 2020-08-28 Migration: vsock support for migration
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20200828a' into staging Migration and virtiofsd pull 2020-08-28 Migration: vsock support for migration minor fixes virtiofsd: Disable remote posix locks by default - because we never supported blocking variants and this breaks things Some prep work for un/less priviliged modes Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> # gpg: Signature made Fri 28 Aug 2020 13:43:18 BST # gpg: using RSA key 45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" [full] # Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7 * remotes/dgilbert/tags/pull-migration-20200828a: virtiofsd: probe unshare(CLONE_FS) and print an error virtiofsd: drop CAP_DAC_READ_SEARCH virtiofsd: Remove "norace" from cmdline help and docs virtiofsd: Disable remote posix locks by default migration: tls: fix memory leak in migration_tls_get_creds migration: improve error reporting of block driver state name migration: add vsock as data channel support migration: unify the framework of socket-type channel Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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ea1bb830 |
| 28-Aug-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200828' into staging target-arm queue: * target/arm: Cleanup and refactoring preparatory to SVE2 * armsse: Def
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200828' into staging target-arm queue: * target/arm: Cleanup and refactoring preparatory to SVE2 * armsse: Define ARMSSEClass correctly * hw/misc/unimp: Improve information provided in log messages * hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize * hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize * hw/net/allwinner-sun8i-emac: Use AddressSpace for DMA transfers * hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers * target/arm: Fill in the WnR syndrome bit in mte_check_fail * target/arm: Clarify HCR_EL2 ARMCPRegInfo type * hw/arm/musicpal: Use AddressSpace for DMA transfers * hw/clock: Minor cleanups * hw/arm/sbsa-ref: fix typo breaking PCIe IRQs # gpg: Signature made Fri 28 Aug 2020 10:23:02 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200828: (35 commits) target/arm: Convert sq{, r}dmulh to gvec for aa64 advsimd target/arm: Convert integer multiply-add (indexed) to gvec for aa64 advsimd target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd target/arm: Generalize inl_qrdmlah_* helper functions target/arm: Tidy SVE tszimm shift formats target/arm: Split out gen_gvec_ool_zz target/arm: Split out gen_gvec_ool_zzz target/arm: Split out gen_gvec_ool_zzp target/arm: Merge helper_sve_clr_* and helper_sve_movz_* target/arm: Split out gen_gvec_ool_zzzp target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp target/arm: Clean up 4-operand predicate expansion target/arm: Merge do_vector2_p into do_mov_p target/arm: Rearrange {sve,fp}_check_access assert target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn target/arm: Split out gen_gvec_fn_zz qemu/int128: Add int128_lshift armsse: Define ARMSSEClass correctly hw/misc/unimp: Display the offset with width of the region size hw/misc/unimp: Display the value with width of the access size ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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5be4dd04 |
| 28-Aug-2020 |
Richard Henderson <richard.henderson@linaro.org> |
qemu/int128: Add int128_lshift Add left-shift to match the existing right-shift. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <pete
qemu/int128: Add int128_lshift Add left-shift to match the existing right-shift. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200815013145.539409-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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