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Searched refs:XCHAL_HAVE_PREFETCH_L1 (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h192 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_hifi/include/variant/
H A Dcore.h192 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ macro
/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h220 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ macro
/openbmc/linux/arch/xtensa/variants/csp/include/variant/
H A Dcore.h220 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ macro
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dcore-isa.h220 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h198 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ macro
/openbmc/linux/arch/xtensa/variants/test_kc705_be/include/variant/
H A Dcore.h221 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h229 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h243 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ macro
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-isa.h294 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 cache */ macro