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Searched refs:Versal (Results 1 – 23 of 23) sorted by relevance

/openbmc/qemu/hw/arm/
H A Dxlnx-versal.c36 static void versal_create_apu_cpus(Versal *s) in versal_create_apu_cpus()
67 static void versal_create_apu_gic(Versal *s, qemu_irq *pic) in versal_create_apu_gic()
140 static void versal_create_rpu_cpus(Versal *s) in versal_create_rpu_cpus()
226 static void versal_create_usbs(Versal *s, qemu_irq *pic) in versal_create_usbs()
308 static void versal_create_sds(Versal *s, qemu_irq *pic) in versal_create_sds()
357 static void versal_create_rtc(Versal *s, qemu_irq *pic) in versal_create_rtc()
796 static void versal_map_ddr(Versal *s) in versal_map_ddr()
870 static void versal_unimp(Versal *s) in versal_unimp()
915 Versal *s = XLNX_VERSAL(dev); in versal_realize()
952 Versal *s = XLNX_VERSAL(obj); in versal_init()
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H A Dxlnx-versal-virt.c34 Versal soc;
/openbmc/linux/Documentation/devicetree/bindings/fpga/
H A Dxlnx,versal-fpga.yaml7 title: Xilinx Versal FPGA driver.
13 Device Tree Versal FPGA bindings for the Versal SoC, controlled
/openbmc/qemu/docs/system/arm/
H A Dxlnx-versal-virt.rst1 Xilinx Versal Virt (``xlnx-versal-virt``)
4 Xilinx Versal is a family of heterogeneous multi-core SoCs
12 The family of Versal SoCs share a single architecture but come in
16 The Xilinx Versal Virt board in QEMU is a model of a virtual board
17 (does not exist in reality) with a virtual Versal SoC without I/O
28 - An RTC (Versal built-in)
116 Versal>
141 Versal>
170 Versal>
227 on this Xilinx Versal Virt board.
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/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dxlnx,zynqmp-reset.yaml7 title: Zynq UltraScale+ MPSoC and Versal reset
13 The Zynq UltraScale+ MPSoC and Versal has several different resets.
27 For list of all valid reset indices for Versal
/openbmc/u-boot/arch/arm/dts/
H A Dversal-mini.dts3 * dts file for Xilinx Versal Mini Configuration
13 model = "Versal MINI";
H A Dversal-mini-emmc1.dts3 * dts file for Xilinx Versal Mini eMMC1 Configuration
17 model = "Xilinx Versal MINI eMMC1";
H A Dversal-mini-emmc0.dts3 * dts file for Xilinx Versal Mini eMMC0 Configuration
17 model = "Xilinx Versal MINI eMMC0";
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dxlnx,versal-wwdt.yaml7 title: Xilinx Versal window watchdog timer controller
13 Versal watchdog intellectual property uses window watchdog mode.
/openbmc/qemu/include/hw/arm/
H A Dxlnx-versal.h40 OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL)
54 struct Versal { struct
/openbmc/u-boot/configs/
H A Dxilinx_versal_virt_defconfig18 CONFIG_SYS_PROMPT="Versal> "
H A Dxilinx_versal_mini_defconfig17 CONFIG_SYS_PROMPT="Versal> "
H A Dxilinx_versal_mini_emmc1_defconfig15 CONFIG_SYS_PROMPT="Versal> "
H A Dxilinx_versal_mini_emmc0_defconfig15 CONFIG_SYS_PROMPT="Versal> "
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dxlnx,versal-clk.yaml7 title: Xilinx Versal clock controller
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dxilinx-versal-cpm.yaml7 title: CPM Host Controller device tree for Xilinx Versal SoCs
/openbmc/linux/Documentation/devicetree/bindings/firmware/xilinx/
H A Dxlnx,zynqmp-firmware.yaml26 - description: For implementations complying for Versal.
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml61 - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
66 - const: xlnx,versal-net-emmc # Versal Net eMMC PHY
/openbmc/linux/drivers/fpga/
H A DKconfig238 tristate "Xilinx Versal FPGA"
242 Xilinx Versal SoC. This driver uses the firmware interface to
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dcdns,macb.yaml30 - xlnx,versal-gem # Xilinx Versal
/openbmc/linux/drivers/pci/controller/
H A DKconfig338 bool "Xilinx Versal CPM PCI controller"
343 Xilinx Versal CPM host bridge.
/openbmc/u-boot/arch/arm/
H A DKconfig906 bool "Support Xilinx Versal Platform"
/openbmc/qemu/
H A DMAINTAINERS1041 Xilinx ZynqMP and Versal
1054 Xilinx Versal OSPI
1060 Xilinx Versal CFI