Searched refs:UVD_VCPU_CNTL__BLK_RST_MASK (Results 1 – 9 of 9) sorted by relevance
748 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; in vcn_v4_0_3_start_dpg_mode()1133 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_3_start()1153 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v4_0_3_start()1154 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_3_start()1158 0, ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_3_start()1300 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v4_0_3_stop()1301 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_3_stop()
937 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK | UVD_VCPU_CNTL__BLK_RST_MASK; in vcn_v4_0_start_dpg_mode()1132 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_start()1159 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v4_0_start()1160 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_start()1163 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_start()1503 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v4_0_stop()1504 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v4_0_stop()
843 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; in vcn_v2_5_start_dpg_mode()1063 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v2_5_start()1083 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v2_5_start()1084 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v2_5_start()1087 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v2_5_start()1424 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v2_5_stop()1425 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v2_5_stop()
966 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK; in vcn_v3_0_start_dpg_mode()1186 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v3_0_start()1203 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v3_0_start()1204 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v3_0_start()1207 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v3_0_start()1566 UVD_VCPU_CNTL__BLK_RST_MASK, in vcn_v3_0_stop()1567 ~UVD_VCPU_CNTL__BLK_RST_MASK); in vcn_v3_0_stop()
2765 #define UVD_VCPU_CNTL__BLK_RST_MASK … macro
118 #define UVD_VCPU_CNTL__BLK_RST_MASK … macro
3824 #define UVD_VCPU_CNTL__BLK_RST_MASK … macro
4072 #define UVD_VCPU_CNTL__BLK_RST_MASK … macro
4111 #define UVD_VCPU_CNTL__BLK_RST_MASK … macro